M0519LE3AE datasheet(34/69 Pages) ETC2

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M0519

Nov. 02, 2016

Page 34 of 69

Rev 1.02

Vector Table

6.2.6.2

When an interrupt is accepted, the processor will automatically fetch the starting address of the

interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base

address is fixed at 0x00000000. The vector table contains the initialization value for the stack

pointer on reset, and the entry point addresses for all exception handlers. The vector number on

previous page defines the order of entries in the vector table associated with exception handler

entry as illustrated in previous section.

Vector Table Word Offset (Bytes)

Description

SP_main

– The Main stack pointer

Vector Number

Exception Entry Pointer using that Vector Number

Table 6-4 Vector Table

Operation Description

6.2.6.3

NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-

Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-

1-to-clear policy, both registers reading back the current enabled state of the corresponding

interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become

Pending, however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it

remains in its Active state until cleared by reset or an exception return. Clearing the enable bit

prevents new activations of the associated interrupt.

NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used

to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register

respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers

reading back the current pended state of the corresponding interrupts. The Clear-Pending

NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register

supporting four interrupts).

The general registers associated with the NVIC are all accessible from a block of memory in the

System Control Space and will be described in next section.

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