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M0519LE3AE Datasheet(PDF) 37 Page - List of Unclassifed Manufacturers |
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M0519LE3AE Datasheet(HTML) 37 Page - List of Unclassifed Manufacturers |
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37 / 69 page ![]() M0519 Nov. 02, 2016 Page 37 of 69 Rev 1.02 1 0 PLLCON[19] 22.1184 MHz 4~12 MHz PLLFOUT 111 011 010 001 4~24 MHz Reserved 4~24 MHz HCLK 22.1184 MHz 000 1/2 1/2 1/2 CLKSEL0[5:3] 1 0 SysTick TMR3 EADC UART0-1 ACMP I2C WDT TMR0 TMR1 TMR2 CPU FMC 10 kHz 111 011 010 001 PLLFOUT Reserved 4~24 MHz 10 kHz 22.1184 MHz 000 CLKSEL0[2:0] SYST_CSR[2] CPUCLK 1/(HCLK_N+1) PCLK CPUCLK HCLK 22.1184 MHz WWDT 10 kHz 1/(EADC_N+1) 11 10 CLKSEL1[1:0] HCLK 1/2048 1/(UART_N+1) 22.1184 MHz 4~24 MHz 01 11 01 00 PLLFOUT 4~24 MHz 22.1184 MHz CLKSEL1[25:24] 1 0 SPI0 CLKSEL1[4] CLKSEL1[5] CLKSEL1[6] HCLK 11 10 01 00 HCLK 4~24 MHz 22.1184 MHz Reserved CLKSEL2[3:2] FRQDIV BOD 10 kHz 11 10 CLKSEL2[17:16] 10 kHz 00 HCLK 1/512 HCLK 1/128 PCLK EPWM1 BPWM0 EPWM0 SPI1 SPI2 PLLFOUT OPA ECAP0 ECAP1 MDU QEI0 QEI1 Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-4 Clock Generator Global View Diagram |
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