CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

DS752F1

7

4.1.2 DMA Controller

The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its

own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the

peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment

controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

The 12-channel (6-line) DAI port supports a wide variety of data input formats. The port is capable of accepting

PCM or IEC61937. Up to 32-bit word lengths are supported. Additionally, support is provided for audio data

input to the DSP via the DAI from an HDMI receiver.

The port has two independent slave-only clock domains. Each data input can be independently assigned to a

clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which

off-loads the task of monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data

to be sample-rate converted via software.

4.2.2 Digital Audio Output Port (DAO)

There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data

rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or

the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be

ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a

192-kHz SPDIF transmitter (data with embedded clock on a single line).

modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external

clock up to 50 MHz in SPI mode. This high clock speed enables very fast code download, control or data

delivery. SCP2 defaults to master mode and is dedicated for booting from external serial Flash memory or for

audio sub-system control.

4.2.4 External Memory Interface

The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus.

4.2.5 General Purpose Input/Output (GPIO)

Many of the CS4970x4 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output,

an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge,

active-low, or active-high.

4.2.6 Phase-locked Loop (PLL)-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the

DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on

the DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference

frequency and can be switched to use the PLL output after overlays have been loaded and configured, either

Table 3. CS4970x4 DSP Memory Sizes

Memory

Type

DSP A

DSP B

X

16K SRAM, 32K ROM

10K SRAM, 8K ROM

Y

24K SRAM, 32K ROM

16K SRAM, 16K ROM

P

8K SRAM, 32K ROM

8K SRAM, 24K ROM