CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

DS752F1

14

5.10 Switching Characteristics — Serial Control Port - SPI Master Mode

.

Figure 4. Serial Control Port - SPI Master Mode Timing

Parameter

Symbol

Min

Typical

Max

Units

maximum speed of the communication port may be limited by the firmware application.

2. See Section 5.7.

3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.

——

MHz

—

11*DCLKP +

(SCP_CLK PERIOD)/2

—ns

SCP_CLK low time

16.9

—

—

ns

SCP_CLK high time

16.9

—

—

ns

Setup time SCP_MISO input

11

—

—

ns

Hold time SCP_MISO input

5—

—

ns

SCP_CLK low to SCP_MOSI output valid

——

11

ns

SCP_CLK low to SCP_CS falling

7—

—

ns

SCP_CLK low to SCP_CS rising

—

11*DCLKP +

(SCP_CLK PERIOD)/2

—ns

Bus free time between active SCP_CS

—

3*DCLKP

—

ns

SCP_CLK falling to SCP_MOSI output high-Z

—

—

20

ns

EE_CS#

SCP_CLK

SCP_MISO

SCP_MOSI

0

12

67

0

56

7

A6

A5

A0

R/W

MSB

LSB

MSB

LSB