CS4970x4 Data Sheet

32-bit High Definition Audio Decoder DSP Family

DS752F1

2

Table of Contents

1 Documentation Strategy ............................................................................................................4

2 Overview .....................................................................................................................................4

2.1 Migrating from CS495xx(3) to CS4970x4 ................................................................................................. 5

2.2 Licensing .................................................................................................................................................. 5

3 Code Overlays ............................................................................................................................5

4 Hardware Functional Description ............................................................................................6

4.1 Coyote DSP Core ..................................................................................................................................... 6

4.1.1 DSP Memory ...............................................................................................................................6

4.1.2 DMA Controller ............................................................................................................................7

4.2 On-chip DSP Peripherals ......................................................................................................................... 7

4.2.1 Digital Audio Input Port (DAI) .......................................................................................................7

4.2.2 Digital Audio Output Port (DAO) ..................................................................................................7

4.2.4 External Memory Interface ..........................................................................................................7

4.2.5 General Purpose Input/Output (GPIO) ........................................................................................7

4.2.6 Phase-locked Loop (PLL)-based Clock Generator ......................................................................7

4.3 DSP I/O Description ................................................................................................................................. 8

4.3.1 Multiplexed Pins ..........................................................................................................................8

4.3.2 Termination Requirements ...........................................................................................................8

4.3.3 Pads ............................................................................................................................................8

4.4 Application Code Security ........................................................................................................................ 8

5 Characteristics and Specifications ..........................................................................................8

5.1 Absolute Maximum Ratings ...................................................................................................................... 8

5.2 Recommended Operating Conditions ...................................................................................................... 9

5.3 Digital DC Characteristics ........................................................................................................................ 9

5.4 Power Supply Characteristics .................................................................................................................. 9

5.5 Thermal Data (128-pin LQFP) ................................................................................................................ 10

5.6 Switching Characteristics—RESET ......................................................................................................... 11

5.7 Switching Characteristics — XTI ............................................................................................................ 11

5.8 Switching Characteristics — Internal Clock ............................................................................................ 12

5.9 Switching Characteristics — Serial Control Port - SPI Slave Mode ....................................................... 13

5.10 Switching Characteristics — Serial Control Port - SPI Master Mode ................................................... 14

5.13 Switching Characteristics — Parallel Control Port - Intel Slave Mode ................................................. 16

5.14 Switching Characteristics — Parallel Control Port - Motorola Slave Mode ......................................... 19

5.15 Switching Characteristics — Digital Audio Slave Input Port ................................................................. 21

5.16 Switching Characteristics — Digital Audio Output Port ........................................................................ 22

5.17 Switching Characteristics — SDRAM Interface .................................................................................... 23

6 Ordering Information ...............................................................................................................27

7 Environmental, Manufacturing, and Handling Information .................................................27

8 Device Pin-Out Diagram ..........................................................................................................28

8.1 128-Pin LQFP Pin-Out Diagram ............................................................................................................. 28

9 Package Mechanical Drawings ...............................................................................................29

9.1 128-Pin LQFP Package Drawing ........................................................................................................... 29

10 Revision History .....................................................................................................................30