EPF8282AV datasheet(32/61 Pages) ALTERA

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Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Timing Model

The continuous, high-performance FastTrack Interconnect routing

structure ensures predictable performance and accurate simulation and

timing analysis. This predictable performance contrasts with that of

FPGAs, which use a segmented connection scheme and hence have

unpredictable performance. Timing simulation and delay prediction are

available with the MAX+PLUS II Simulator and Timing Analyzer, or with

industry-standard EDA tools. The Simulator offers both pre-synthesis

functional simulation to evaluate logic design accuracy and post-

synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer

provides point-to-point timing delay information, setup and hold time

prediction, and device-wide performance analysis.

Tables 8 through 11 describe the FLEX 8000 timing parameters and their

symbols.

Table 8. FLEX 8000 Internal Timing Parameters

Note (1)

Symbol

Parameter

tIOD

IOE register data delay

tIOC

IOE register control signal delay

tIOE

Output enable delay

tIOCO

IOE register clock-to-output delay

tIOCOMB IOE combinatorial delay

tIOSU

IOE register setup time before clock; IOE register recovery time after asynchronous clear

tIOH

IOE register hold time after clock

tIOCLR

IOE register clear delay

tIN

Input pad and buffer delay

tOD1

Output buffer and pad delay, slow slew rate = off, VCCIO = 5.0 V, C1 = 35 pF, Note (2)

tOD2

Output buffer and pad delay, slow slew rate = off, VCCIO = 3.3 V, C1 = 35 pF, Note (2)

tOD3

Output buffer and pad delay, slow slew rate = on, C1 = 35 pF,

Note (3)

tXZ

Output buffer disable delay, C1 = 5 pF

tZX1

Output buffer enable delay, slow slew rate = off, VCCIO = 5.0 V, C1 = 35 pF, Note (2)

tZX2

Output buffer enable delay, slow slew rate = off, VCCIO = 3.3 V, C1 = 35 pF, Note (2)

tZX3

Output buffer enable delay, slow slew rate = on, C1 = 35 pF,

Note (3)

EPF8282AV Datasheet(PDF) 32 Page - Altera Corporation

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