EPF8282AV datasheet(34/61 Pages) ALTERA

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Altera Corporation

FLEX 8000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1)

Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and

external parameters specified by Altera. Internal timing parameters should be used for estimating device

performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case

performance.

(2)

These values are specified under “FLEX 8000 3.3-V Device Recommended Operating Conditions” on page 29.

(3)

For the tOD3 and tZX3 parameters, VCCIO = 3.3 V or 5.0 V.

(4)

The tROW and tDIN_D delays are worst-case values for typical applications. Post-compilation timing simulation or

timing analysis is required to determine actual worst-case performance.

(5)

External reference timing characteristics are factory-tested, worst-case values specified by Altera. A representative

subset of signal paths is tested to approximate typical device applications.

(6)

For more information on test conditions, see Application Note 76 (Understanding FLEX 8000 Timing) in this data book.

(7)

This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This

parameter applies to global and non-global clocking, and for LE and I/O element registers.

The FLEX 8000 timing model shows the delays for various paths and

functions in the circuit. See Figure 19. This model contains three distinct

parts: the LE; the IOE; and the interconnect, including the row and column

FastTrack Interconnect, LAB local interconnect, and carry and cascade

interconnect paths. Each parameter shown in Figure 19 is expressed as a

worst-case value in the “Timing Parameters” tables in this data sheet.

Hand-calculations that use the FLEX 8000 timing model and these timing

parameters can be used to estimate FLEX 8000 device performance.

Timing simulation or timing analysis after compilation is required to

determine the final worst-case performance. Table 12 summarizes the

interconnect paths shown in Figure 19.

f For more information on timing parameters, go to Application Note 76

(Understanding FLEX 8000 Timing) in this data book.

Table 12. FLEX 8000 Timing Model Interconnect Paths

Source

Destination

Total Delay

LE-Out

LE in same LAB

tLOCAL

LE-Out

LE in same row, different LAB

tROW + tLOCAL

LE-Out

LE in different row

tCOL + tROW + tLOCAL

LE-Out

IOE on column

tCOL

LE-Out

IOE on row

tROW

IOE on row

LE in same row

tROW + tLOCAL

IOE on column

Any LE

tCOL + tROW + tLOCAL

EPF8282AV Datasheet(PDF) 34 Page - Altera Corporation

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