PC87372 datasheet(42/144 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

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Revision 1.2

3.7.5

SuperI/O Revision ID Register (SRID)

This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). The

PC87372 is identified by the value ‘000’. The Chip Rev is incremented on each revision.

Power Well: VSB3

Location:

Index 27h

Type:

R/W or

SERDIS (Serial Port Disable). When set to 1, this bit forces the Serial Port module to be disabled (and

its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

−

Reserved.

R/W or

PARPDIS (Parallel Port Disable). When set to 1, this bit forces the Parallel Port module to be disabled

(and its resources released) regardless of the actual setting of its Activation bit (index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

R/W or

FDCDIS (Floppy Disk Controller Disable). When set to 1, this bit forces the Floppy Disk Controller

module to be disabled (and its resources released) regardless of the actual setting of its Activation bit

(index 30).

0: Enabled or Disabled, according to Activation bit (default)

1: Disabled

Bit

76543210

Name

Chip ID

Chip Rev

Reset

XXXXX

Bit

Description

7-5

Chip ID. These bits identify a specific device of a family.

4-0

Chip Rev. These bits identify the device revision.

Bit

Type

Description

PC87372 Datasheet(PDF) 42 Page - National Semiconductor (TI)

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