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PC87372 Datasheet(PDF) 18 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87372
Description  LPC SuperI/O with Glue Functions
PDF  144 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87372 Datasheet(HTML) 18 Page - National Semiconductor (TI)

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1.0 Signal/Pin Connection and Description (Continued)
18
www.national.com
Revision 1.2
1.4.5
Keyboard and Mouse Controller (KBC)
1.4.6
General-Purpose I/O (GPIO)
1.4.7
Fan Speed Monitor (FSM)
Signal
Pin(s)
I/O Buffer Type Power Well
Description
KBCLK
3
I/O
INTS/OD14
VDD3
Keyboard Clock. Keyboard clock signal. External pull-up resistor
is required for PS/2 compliance. This pin is monitored during
VDD3 power-off for wake-up event detection.
KBDAT
4
I/O
INTS/OD14
VDD3
Keyboard Data. Keyboard data signal. External pull-up resistor is
required for PS/2 compliance. This pin is monitored during VDD3
power-off for wake-up event detection.
MCLK
1
I/O
INTS/OD14
VDD3
Mouse Clock. Mouse clock signal. External pull-up resistor is
required for PS/2 compliance. This pin is monitored during VDD3
power-off for wake-up event detection.
MDAT
2
I/O
INTS/OD14
VDD3
Mouse Data. Mouse data signal. External pull-up resistor is
required for PS/2 compliance. This pin is monitored during VDD3
power-off for wake-up event detection.
KBRST
7
I/O
INT/OD8,
O4/8
VDD3
KBD Reset. Keyboard reset (P20) quasi-bidirectional output.
GA20
5
I/O
INT/OD8,
O4/8
VDD3
Gate A20. KBC gate A20 (P21) quasi-bidirectional output.
Signal
Pin(s)
I/O Buffer Type Power Well
Description
GPIOE00-07 103-106,
108-109,
111-112
I/O
INTS/
OD8,O4/8
VSB3
General-Purpose I/O Ports. Each pin is configured
independently as input or I/O, with or without static pull-up and
with either open-drain or push-pull output type. These pins
have event detection capability to generate a wake-up event
or an interrupt.
GPIOE10-13 116, 114,
115, 113
GPIO14
101
I/O
INTS/
OD12,O2/12
General-Purpose I/O Port. This pin is configured
independently as input or I/O with or without static pull-up and
with either open-drain or push-pull output type.
Signal
Pin(s)
I/O Buffer Type Power Well
Description
FANTACH1
FANTACH2
111,
112
IINTS
VDD3
Fan Tachometer Inputs. Input to the Fan Speed Monitor for the
fan tachometer pulse. The rising edge indicates the completion of
either a half or full fan revolution.



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