PC87372 datasheet(5/144 Pages) NSC

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Revision 1.2

Table of Contents

1.0

Signal/Pin Connection and Description

1.1

CONNECTION DIAGRAMS

................................................................................................ 11

1.2

BUFFER TYPES AND SIGNAL/PIN DIRECTORY .................................................................... 12

1.3

PIN MULTIPLEXING ................................................................................................................. 13

1.4

DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 14

1.4.1

LPC Interface ..............................................................................................................14

1.4.2

Serial Port (UART)

.................................................................................................. 15

1.4.3

Parallel Port

..............................................................................................................16

1.4.4

Floppy Disk Controller (FDC)

.................................................................................... 17

1.4.5

Keyboard and Mouse Controller (KBC)

..................................................................... 18

1.4.6

General-Purpose I/O (GPIO) ...................................................................................... 18

1.4.7

Fan Speed Monitor (FSM)

......................................................................................... 18

1.4.8

System Wake-Up Control (SWC)

.............................................................................. 19

1.4.9

Clocks

.....................................................................................................................19

1.4.10

Glue Functions ........................................................................................................... 20

1.4.11

Configuration Straps and Testing ............................................................................... 21

1.4.12

Power and Ground

.................................................................................................... 22

1.5

INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 22

2.0

Power, Reset and Clocks

2.1

POWER ..................................................................................................................................... 24

2.1.1

Power Planes .............................................................................................................. 24

2.1.2

Power States ...............................................................................................................24

2.1.3

Power Connection and Layout Guidelines .................................................................. 25

2.2

RESET SOURCES AND TYPES ............................................................................................... 26

2.2.1

VSB Power-Up Reset .................................................................................................. 26

2.2.2

VDD Power-Up Reset .................................................................................................. 27

2.2.3

Hardware Reset ........................................................................................................... 27

2.2.4

Software Reset ............................................................................................................ 27

2.3

CLOCK DOMAINS ..................................................................................................................... 27

2.3.1

LPC Domain ................................................................................................................ 27

2.3.2

48 MHz Domain ........................................................................................................... 28

2.3.3

32 KHz Domain ........................................................................................................... 28

2.4

TESTABILITY SUPPORT ..........................................................................................................28

2.4.1

ICT ............................................................................................................................... 28

2.4.2

XOR Tree Testing ........................................................................................................ 29

3.0

Device Architecture and Configuration

3.1

OVERVIEW ............................................................................................................................... 30

3.2

CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 30

3.2.1

The Index-Data Register Pair ...................................................................................... 30

3.2.2

Banked Logical Device Registers Structure ................................................................ 31

3.2.3

Standard Configuration Register Definitions ............................................................... 32

3.2.4

Standard Configuration Registers

............................................................................ 34

3.2.5

Default Configuration Setup ........................................................................................ 35

PC87372 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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