PC87372 datasheet(109/144 Pages) NSC

109 / 144 page

8.0 Glue Functions (Continued)

109

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The 3V_DDCSCL and 5V_DDCSCL pins are connected through a switch. This switch is controlled by a Level Translation

Control circuit, according to the voltage levels at the 3V_DDCSCL and 5V_DDCSCL pins (for the DC characteristics, see

Section 10.2.10 on page 125):

For VIN <VISC at either pin, the switch is closed; therefore, both pins (3V_DDCSCL, and 5V_DDCSCL) are held at

low level.

For VIN >VISO at both pins, the switch is open; therefore, each pin is pulled up to high level by the external resistor

connected to VDD3 (for the 3V_DDCSCL pin) and to VDD5 (for the 5V_DDCSCL pin).

In addition, when the VDD3 power is off, the switch is open, regardless of the voltage levels at the 3V_DDCSCL and

5V_DDCSCL pins.

The 3V_DDCSDA and 5V_DDCSDA pins are connected through a similar level translation circuit and behave like

3V_DDCSCL and 5V_DDCSCL.

Figure 30 shows a simplified diagram of the circuit that performs SMBus voltage translation.

Figure 30. SMBus Voltage Translation (Simpliﬁed Diagram)

For the AC characteristics, see SMBus Voltage Translation and Isolation Timing on page 142.

8.2.11 SMBus Isolation

When the Main power is off, this function performs “passive” bus isolation between the SMB1_SCL, SMB1_SDA signals and

the SMB2_SCL, SMB2_SDA signals respectively. The bus isolation enables the operation of the serial bus section connect-

ed to Standby power, if the other serial bus is connected to the Main power and the Main power is off.

The signals connected to the SMB1_SCL, SMB1_SDA, SMB2_SCL and SMB2_SDA pins are compatible Intel's SMBus

(Speciﬁcation Rev 1.1, Dec. 11, 1998) two-wire synchronous serial interface speciﬁcations.

The SMB1_SCL and SMB2_SCL pins are connected through a switch. This switch is controlled by the voltage levels at the

SMB1_SCL and SMB2_SCL pins (for the DC characteristics, see Section 10.2.10 on page 125):

For VIN <VISC at either pin, the switch is closed; therefore, both pins (SMB1_SCL, and SMB2_SCL) are held at low

level.

For VIN >VISO at both pins, the switch is open; therefore, each pin is pulled up to high level by the external resistor

connected to VSUP1 (for the SMB1_SCL pin) and to VSUP2 (for the SMB2_SCL pin).

In addition, when the Main power supply voltage is not valid (PWRGD_PS = low), the switch is forced open and the unpow-

ered SMBx_SCL signal is disconnected from the powered SMBx_SCL signal (x is either 1 or 2). This isolation between the

two signals prevents the loading of the powered SMBx_SCL signal by the unpowered SMBx_SCL signal.

The SMB1_SDA and SMB2_SDA pins are connected through a similar level isolation circuit and behave like SMB1_SCL

and SMB2_SCL.

Figure 31 shows a simplified diagram of the circuit that performs SMBus isolation.

Figure 31. SMBus Isolation (Simpliﬁed Diagram)

For the AC characteristics, see SMBus Voltage Translation and Isolation Timing on page 142.

2.2 K

Ω

5V_DDCSnn

VDD5

4.7 K

Ω

3V_DDCSnn

VDD3

Snn = SCL or SDA

Level

Control

Translation

2.7 K

Ω

SMB2_Snn

VSUP2 (3.3V)

2.7 K

Ω

SMB1_Snn

VSUP1 (3.3V)

Snn = SCL or SDA

Control

Switch

PWRGD_PS

PC87372 Datasheet(PDF) 109 Page - National Semiconductor (TI)

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