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PC87372 Datasheet(PDF) 123 Page - National Semiconductor (TI) |
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PC87372 Datasheet(HTML) 123 Page - National Semiconductor (TI) |
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123 / 144 page  10.0 Device Characteristics (Continued) 123 www.national.com Revision 1.2 10.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES The following tables summarize the DC characteristics of all device pins described in Section 1.2 on page 12. The charac- teristics describe the general I/O buffer types defined in Table 1 on page 12. For exceptions, refer to Section 10.2.11 on page 125. The DC characteristics of the LPC interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling. 10.2.1 Input, TTL Compatible Symbol: INT 10.2.2 Input, TTL Compatible, with Schmitt Trigger Symbol: INTS 10.2.3 Input, TTL Compatible, with 400 mV Schmitt Trigger Symbol: INTS4 Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V IIL 2 2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0<VIN <VSUP 3 3. VSUP is VDD3 or VSB3 according to the input power well. ±14 4. Maximum 20 µA for all pins together (for exceptions, refer to Section 10.2.11 on page 125). Not tested. Guaran- teed by characterization. µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V VHY Input Hysteresis 2502 2. Not tested. Guaranteed by characterization. mV IIL 3 3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0<VIN <VSUP 4 4. VSUP is VDD3 or VSB3 according to the input power well. ±15 5. Maximum 20 µA for all pins together (for exceptions, refer to Section 10.2.11 on page 125.). Not tested. Guaran- teed by characterization. µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V VHY Input Hysteresis 4002 2. Not tested. Guaranteed by characterization. mV IIL 3 3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0<VIN <VSUP 4 4. VSUP is VDD3 or VSB3 according to the input power well. ±15 5. Maximum 20 µA for all pins together (for exceptions, refer to Section 10.2.11 on page 125.). Not tested. Guaran- teed by characterization. µA |
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