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PC87372 Datasheet(PDF) 142 Page - National Semiconductor (TI) |
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PC87372 Datasheet(HTML) 142 Page - National Semiconductor (TI) |
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142 / 144 page  10.0 Device Characteristics (Continued) 142 www.national.com Revision 1.2 Figure 46. BKFD_CUT and LATCHED_BF_CUT (AC Characteristics) Main Power Supply Control CNR Downstream Codec Dynamic Control SMBus Voltage Translation and Isolation Timing Symbol Figure Description Reference Conditions Min Max Units tPR − Rise Propagation Delay1 1. Not tested. Guaranteed by design. CPU_PRESENT or SLP_S3 to RE of PS_ON 1 µs tPF − Fall Propagation Delay1 CPU_PRESENT or SLP_S3 to FE of PS_ON 1 µs tR − Rise Time1 0.8V to 2.0V 50 ns tF − Fall Time1 0.8V to 2.0V 50 ns Symbol Figure Description Reference Conditions Min Max Units tPD − Propagation Delay1 1. Not tested. Guaranteed by characterization. AUD_LINK_RST to CDC_DWN_RST 30 ns tTR − Transition Time1 0.8V to 2.0V 15 ns Symbol Figure Description Type of Requirement1 1. An “Input” type is a value the PC87372 device expects from the system; an “Output” type is a value the PC87372 device provides to the system. Min Max Unit tSMBR − Rise Time (all signals) Input 10002,3 2. Test conditions: RL = 1 KΩ to VDD3 = 3.3V, or RL = 1.5 KΩ to VDD5 = 5V and CL = 400 pF to GND. 3. Not tested. Guaranteed by design. ns tSMBF − Fall Time (all signals) Input 2503 ns Output 3002,4 4. Not tested. Guaranteed by characterization. ns tSMBD − Propagation Delay (each signal pair, in both directions) Output 5002,4 ns 0.8V 1.4V 2.0V SLP_S5 BKFD_CUT LATCHED_BF_CUT tPL tTL 0.8V tPL 1.4V tTL 2.0V tPL tPL |
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