| Electronic Components Datasheet Search |
|
68HC908RF Datasheet(PDF) 71 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
68HC908RF Datasheet(HTML) 71 Page - Motorola, Inc |
|
71 / 188 page ![]() Internal Clock Generator Module (ICG) Functional Description MC68HC908RF2 — Rev. 4.0 Data Sheet MOTOROLA Internal Clock Generator Module (ICG) 71 The amplifier is enabled when the ECGON bit is set and stop mode is not enabled. When the amplifier is enabled, it will be connected between the OSC1 and OSC2 pins. In its typical configuration, the external oscillator requires five external components: 1. Crystal, X1 2. Fixed capacitor, C1 3. Tuning capacitor, C2 (can also be a fixed capacitor) 4. Feedback resistor, RB 5. Series resistor, RS (included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals). Refer to the crystal manufacturer’s data for more information. 6.3.3.2 External Clock Input Path The external clock input path is the means by which the microcontroller uses an external clock source. The input to the path is the OSC1 pin and the output is the external clock (ECLK). The path, which contains input buffering, is enabled when the ECGON bit is set and stop mode is not enabled. 6.3.4 Clock Monitor Circuit The ICG contains a clock monitor circuit which, when enabled, will continuously monitor both the external clock (ECLK) and the internal clock (ICLK) to determine if either clock source has failed based on these conditions: • Either ICLK or ECLK has stopped. • The frequency of IBASE < frequency EREF divided by 4 • The frequency of ECLK < frequency of IREF divided by 4 Using the clock monitor requires both clocks to be active (ECGON and ICGON are both set). To enable the clock monitor, both clocks must also be stable (ECGS and ICGS both set). This is to prevent the use of the clock monitor when a clock is first turned on and potentially unstable NOTE: Although the clock monitor can be enabled only when the both clocks are stable (ICGS or ECGS is set), the clock monitor will remain enabled if one of the clocks goes unstable. The clock monitor only works if the external slow (EXTSLOW) bit in the configuration register is properly defined with respect to the external frequency source. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |