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68HC908RF Datasheet(PDF) 30 Page - Motorola, Inc

Part # 68HC908RF
Description  Microcontrollers
PDF  188 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

68HC908RF Datasheet(HTML) 30 Page - Motorola, Inc

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Memory
Data Sheet
MC68HC908RF2 — Rev. 4.0
30
Memory
MOTOROLA
BLK0 — Block Erase Control Bit
This read/write bit together with BLK1 allows erasing of blocks of varying size.
See 2.5.3 FLASH 2TS Erase Operation for a description of available block
sizes.
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program
and erase operations in the array. HVEN can be set only if either PGM = 1 or
ERASE = 1 and the proper sequence for smart programming or erase is
followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MARGIN — Margin Read Control Bit
This read/write bit configures the memory for margin read operation. MARGIN
cannot be set if the HVEN = 1. MARGIN will automatically return to unset (0) if
asserted when HVEN = 1.
1 = Margin read operation selected
0 = Margin read operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is
interlocked with the PGM bit such that both bits cannot be set at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is
interlocked with the ERASE bit such that both bits cannot be set at the same
time.
1 = Program operation selected
0 = Program operation unselected
2.5.2 FLASH 2TS Charge Pump Frequency Control
The internal charge pump, required for program, margin read, and erase
operations, is designed to operate most efficiently with a 2-MHz clock. The charge
pump clock is derived from the bus clock. Table 2-2 shows how the FDIV bits are
used to select a charge pump frequency based on the bus clock frequency.
Program, margin read, and erase operations cannot be performed if the bus clock
frequency is below 2 MHz.
NOTE:
The charge pump is optimized for 2-MHz operation.
Table 2-2. Charge Pump Clock Frequency
FDIV0
Pump Clock Frequency
0
Bus frequency
÷ 1
1
Bus frequency
÷ 2
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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