AD9253 datasheet(28/41 Pages) AD

28 / 41 page

Data Sheet

AD9253

Rev. B | Page 27 of 40

500

400

300

200

100

–500

–400

–300

–200

–100

–0.8ns

–0.4ns

0ns

0.4ns

–0.8ns

EYE: ALL BITS

ULS: 8000/414024

10k

12k

–800ps –600ps –400ps –200ps

0ps

200ps

400ps

600ps

Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths

Greater than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End

Termination Only

Figure 73 shows an example of trace lengths exceeding 24 inches

on standard FR-4 material. Notice that the TIE jitter histogram

reflects the decrease of the data eye opening as the edge deviates

from the ideal position. It is the user’s responsibility to determine

if the waveforms meet the timing budget of the design when the

trace lengths exceed 24 inches. Additional SPI options allow the

user to further increase the internal termination (increasing the

current) of all four outputs to drive longer trace lengths. This can

be achieved by programming Register 0x15. Even though this

produces sharper rise and fall times on the data edges and is less

prone to bit errors, the power dissipation of the DRVDD supply

increases when this option is used.

The format of the output data is twos complement by default.

An example of the output coding format can be found in Table 10.

To change the output data format to offset binary, see the

Memory Map section.

Data from each ADC is serialized and provided on a separate

channel in two lanes in DDR mode. The data rate for each serial

stream is equal to 16 bits times the sample clock rate divided by

the number of lanes, with a maximum of 1000 Mbps/lane

[(16 bits × 125 MSPS)/2 = 1000 Mbps/lane)]. The maximum

allowable output data rate is 1 Gbps/lane. If one-lane mode is

used, the data rate doubles for a given sample rate. To stay

within the maximum data rate of 1 Gbps/lane, the sample rate is

limited to a maximum of 62.5 MSPS in one-lane output mode.

The lowest typical conversion rate is 10 MSPS.

Two output clocks are provided to assist in capturing data from

the AD9253. The DCO is used to clock the output data and is

equal to four times the sample clock (CLK) rate for the default

mode of operation. Data is clocked out of the AD9253 and must

be captured on the rising and falling edges of the DCO that

supports double data rate (DDR) capturing. The FCO is used to

signal the start of a new output byte and is equal to the sample

clock rate in 1× frame mode. See the Timing Diagrams section

for more information.

Table 10. Digital Output Coding

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

VIN+ − VIN−

<−VREF − 0.5 LSB

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

−VREF

0000 0000 0000 0000

1000 0000 0000 0000

VIN+ − VIN−

0 V

1000 0000 0000 0000

0000 0000 0000 0000

VIN+ − VIN−

+VREF − 1.0 LSB

1111 1111 1111 1100

0111 1111 1111 1100

VIN+ − VIN−

>+VREF − 0.5 LSB

1111 1111 1111 1100

0111 1111 1111 1100

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