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AD9219 Datasheet(PDF) 23 Page - Analog Devices

Part # AD9219
Description  Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC
PDF  57 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9219 Datasheet(HTML) 23 Page - Analog Devices

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AD9219
Data Sheet
Rev. E | Page 22 of 56
For best dynamic performance, the source impedances driving
VIN + x and VIN − x should be matched such that common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal
reference buffer creates the positive and negative reference
voltages, REFT and REFB, respectively, that define the span of
the ADC core. The output common-mode of the reference buffer
is set to midsupply, and the REFT and REFB voltages and span
are defined as
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9219, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9219 either actively or
passively; however, optimum performance is achieved by driving
the analog input differentially. For example, using the AD8332
differential driver to drive the AD9219 provides excellent perfor-
mance and a flexible interface to the ADC (see Figure 51) for
baseband applications. This configuration is commonly used
for medical ultrasound systems.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 48 and Figure 49), because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9219.
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
2V p-p
R
R
*CDIFF
C
*CDIFF IS OPTIONAL
49.9Ω
0.1μF
1kΩ
1kΩ
AGND
AVDD
ADT1-1WT
1:1 Z RATIO
VIN – x
ADC
AD9219
VIN + x
C
Figure 48. Differential Transformer-Coupled Configuration
for Baseband Applications
ADC
AD9219
2V p-p
2.2pF
1kΩ
0.1μF
1kΩ
1kΩ
AVDD
ADT1-1WT
1:1 Z RATIO
16nH
16nH
0.1μF
16nH
33Ω
33Ω
499Ω
65Ω
VIN + x
VIN – x
Figure 49. Differential Transformer-Coupled Configuration
for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the application requires a single-ended input configuration,
ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale
input of 2 V p-p can be applied to the ADC’s VIN + x pin while the
VIN − x pin is terminated. Figure 50 details a typical single-
ended input configuration.
2V p-p
R
R
49.9Ω
0.1µF
0.1µF
AVDD
1kΩ 25Ω
1kΩ
1kΩ
AVDD
VIN – x
ADC
AD9219
VIN + x
*CDIFF
C
*CDIFF IS OPTIONAL
C
Figure 50. Single-Ended Input Configuration
AD8332
1kΩ
187Ω
187Ω
0.1μF
0.1μF
0.1μF
1V p-p
0.1μF
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF
274Ω
VIN – x
ADC
AD9219
VIN + x
LPF
+
68pF
33Ω
33Ω
AVDD
AVDD
680nH
680nH
10kΩ
10kΩ
10kΩ
10kΩ
Figure 51. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter



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