AD9219 datasheet(25/57 Pages) AD

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AD9219

Data Sheet

Rev. E | Page 24 of 56

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (fA)

due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter. IF undersampling applications

are particularly sensitive to jitter (see Figure 57).

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9219.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators are

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock during the last step.

Refer to the AN-501 Application Note and to the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs at www.analog.com.

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125 ps

0.25 ps

0.5 ps

1.0 ps

2.0 ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

RMS CLOCK JITTER REQUIREMENT

Figure 57. Ideal SNR vs. Input Frequency and Jitter

Power Dissipation and Power-Down Mode

As shown in Figure 58 and Figure 59, the power dissipated by

the AD9219 is proportional to its sample rate. The digital power

dissipation does not vary significantly because it is determined

primarily by the DRVDD supply and bias current of the LVDS

output drivers.

ENCODE (MSPS)

AVDD CURRENT

TOTAL POWER

DRVDD CURRENT

180

200

220

240

260

280

300

320

340

360

100

120

140

Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS

ENCODE (MSPS)

AVDD CURRENT

TOTAL POWER

DRVDD CURRENT

100

120

140

160

180

200

250

270

290

310

330

350

370

390

Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS

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