Programmable DC-Balance

21-Bit Deserializers

8

_______________________________________________________________________________________

IDEAL

MIN

MAX

INTERNAL STROBE

IDEAL

RSKM

RSKM

IDEAL SERIAL BIT TIME

1.3V

1.1V

Figure 4. LVDS Receiver Input Skew Margin

RxOUT_

RxCLK OUT

RCIP

RCOH

RCOL

2.0V

0.8V

2.0V

0.8V

2.0V

2.0V

2.0V

0.8V

0.8V

RHRC

RSRC

Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times

RxOUT_

RxCLK OUT

RCIP

RCOH

RCOL

2.0V

0.8V

2.0V

0.8V

2.0V

2.0V

0.8V

0.8V

0.8V

RHRC

RSRC

Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times

1.5V

RCCD

RxCLK IN

RxCLK OUT

Figure 6a. Rising-Edge Clock-IN to Clock-OUT Delay

RxCLK IN

RxCLK OUT

+

-

RCCD

1.5V

Figure 6b. Falling-Edge Clock-IN to Clock-OUT Delay

90%

90%

10%

10%

CHLT

CLHT

RxOUT_ OR

RxCLK OUT

RxOUT_ OR

RxCLK OUT

8pF

Figure 3. Output Load and Transition Times

PWRDWN

RxCLK IN

RxCLK OUT

3V

2V

RPLLS

HIGH-Z

Figure 7. Phase-Locked Loop Set Time