Programmable DC-Balance

21-Bit Deserializers

14

______________________________________________________________________________________

5V Tolerant Input

PWRDWN is 5V tolerant and is internally pulled down to

GND. DCB/NC is not 5V tolerant. The input voltage

Skew Margin (RSKM)

Skew margin (RSKM) is the time allowed for degrada-

tion of the serial data sampling setup and hold times by

sources other than the deserializer. The deserializer

sampling uncertainty is accounted for and does not

need to be subtracted from RSKM. The main outside

contributors of jitter and skew that subtract from RSKM

are interconnect intersymbol interference, serializer

pulse position uncertainty, and pair-to-pair path skew.

to systems with 1.8V to 5V nominal input logic levels. The

DC Electrical Characteristics table gives the maximum

switching frequencies with all outputs switching in the

worst-case switching pattern. The approximate incremen-

8pF load and worst-case pattern can be calculated using:

where:

tance.

Characteristics table maximum supply current. The

worst-case pattern switching frequency of the data out-

puts is half the switching frequency of the output clock.

In the following example, the incremental supply current is

where:

output).

34MHz).

The maximum supply current in DC-balanced mode for

DC Electrical Characteristics table). Add 10.4mA to get

the reduced supply current can be calculated using the

same formula and method.

At high switching frequency, high supply voltage, and

high capacitive loading, power dissipation can exceed

the package power dissipation rating. Do not exceed

the maximum package power dissipation rating. See

the Absolute Maximum Ratings for maximum package

power dissipation capacity and temperature derating.

Rising- or Falling-Edge Output Strobe

The MAX9210/MAX9212/MAX9214/MAX9216 have a

rising-edge output strobe, which latches the parallel

output data into the next chip on the rising edge of

RxCLK OUT. The MAX9220/MAX9222 have a falling-

edge output strobe, which latches the parallel output

data into the next chip on the falling edge of RxCLK

OUT. The deserializer output strobe polarity does not

need to match the serializer input strobe polarity. A

deserializer with rising or falling edge output strobe can

be driven by a serializer with a rising edge input strobe.

RxIN0+

LVDS DATA

RECEIVER 0

RxIN0-

STROBE

DATA

CHANNEL 0

RxOUT0–6

SERIAL-TO-

PARALLEL

CONVERTER

RxIN1+

LVDS DATA

RECEIVER 1

RxIN1-

STROBE

DATA

CHANNEL 1

RxOUT7–13

SERIAL-TO-

PARALLEL

CONVERTER

RxIN2+

LVDS DATA

RECEIVER 2

RxIN2-

STROBE

DATA

CHANNEL 2

RxOUT14–20

SERIAL-TO-

PARALLEL

CONVERTER

RxCLK IN+

LVDS CLOCK

RECEIVER

RxCLK IN-

DCB/NC

7x/9x

PLL

RxCLK OUT

REFERENCE

CLOCK

GENERATOR

PWRDWN

Functional Diagram