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AD9877 Datasheet(PDF) 16 Page - Analog Devices

Part # AD9877
Description  Set-Top Box, Cable Modem
PDF  37 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9877 Datasheet(HTML) 16 Page - Analog Devices

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AD9877
Rev. B | Page 15 of 36
PROGRAMMABLE CLOCK OUTPUT REFCLK
The AD9877 provides a frequency-programmable clock output
REFCLK (Pin 71). OSCIN or MCLK (fMCLK) and the master
clock divider ratio R stored in Register Address 0x01 determine
its frequency.
fOSCOUT = fMCLK/R or fOSCIN
In its default setting (0x00 in Register 0x01), the REFCLK pin
provides a buffered output of fOSCIN.
2
DRGND
3
DRVDD
4
(MSB) IF(11)
7
IF(8)
6
IF(9)
5
IF(10)
1
AVDD
8
IF(7)
9
IF(6)
10
IF(5)
12
IF(3)
13
IF(2)
14
IF(1)
15
IF(0)
16
(MSB) RxIQ(3)
17
RxIQ(2)
18
RxIQ(1)
19
RxIQ(0)
20
RxSYNC
21
DRGND
22
DRVDD
23
MCLK
24
DVDD
25
DGND
26
TxSYNC
27
(MSB) TxIQ(5)
28
TxIQ(4)
29
TxIQ(3)
30
TxIQ(2)
11
IF(4)
79
I IN+
78
I IN–
77
AGNDIQ
74
AGNDIQ
75
NC
76
NC
80
AGNDIQ
73
AVDDIQ
72
DRVDD
71
REFCLK
69
DGNDSD
68
SDELTA0
67
SDELTA1
66
DVDDSD
65
CA_EN
64
CA_DATA
63
CA_CLK
62
DVDDOSC
61
OSCIN
60
XTAL
59
DGNDOSC
58
AGNDPLL
57
PLLFILT
56
AVDDPLL
55
DVDDPLL
54
DGNDPLL
53
AVDDTx
52
Tx+
51
Tx–
70
DRGND
PIN 1
AD9877
TOP VIEW
(Pins Down)
NC = NO CONNECT
C3
0.1
μF
C6
0.1
μF
C1
0.1
μF
C4
0.1
μF
CP1
10
μF
CP2
10
μF
C2
0.1
μF
C5
0.1
μF
C10
20pF
C11
20pF
GUARD TRACE
C12
0.01
μF
R1
1.3k
Ω
C13
0.1
μF
RSET
2k
Ω
Figure 16. Basic Connection Diagram



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