AD9877 datasheet(21/37 Pages) AD

21 / 37 page

AD9877

Rev. B | Page 20 of 36

Bit 4: Power-Down RxSYNC and 8-Bit ADC Clock

Setting this bit to 1 powers down the sampling clock of the 8-bit

ADC and stops the RxSYNC output pin. It can be used for

additional power saving on top of the power-down selections in

Bit 7: ADC Clock Select

When set high, the input clock at OSCIN is used directly as the

ADC sampling clock. When set low, the internally generated

master clock, MCLK, is used as the ADC sampling clock. Best

ADC performance is achieved when the ADCs are sampled

directly from fOSCIN using an external crystal or low jitter crystal

oscillator.

Bits 0–3: Version

The die version of the chip can be read from this register.

LSBs

This register accommodates 2 LSBs for each of the four

frequency tuning words (see the Registers 0X10–0X1F—Burst

Parameter section).

This register allows the user to program the DAC gain if Tx

Gain Control Select Bit 3 in Register 0x0F is set to 0.

Table 6. DAC Gain Control

Bits [3:0]

DAC Gain

0000

0.0 dB (default)

0001

0.5 dB

0010

1.0 dB

0011

1.5 dB

...

1110

7.0 dB

1111

7.5 dB

Bit 0: Single-Tone Tx Mode

Active high configures the AD9877 for single-tone applications

such as FSK. The AD9877 will supply a single-frequency output

as determined by the frequency tuning word selected by the

active profile. In this mode, the TxIQ input data pins are

ignored but should be tied to a valid logic voltage level. Default

value is 0 (inactive).

Bit 1: Spectral Inversion Tx

When set to 1, inverted modulation is performed.

MODULATOR_OUT = [I cos(ωt) + Q sin(ωt)]

Default is logic low, noninverted modulation.

MODULATOR_OUT = [I cos(ωt) − Q sin(ωt)]

Bit 3: CA Interface Mode Select

This bit changes the manner in which transmit gain control is

performed. Typically, either AD8321/AD8325 (Default 0) or

AD8322/AD8327 (Default 1) variable gain cable amplifiers are

programmed over the chip’s 3-wire cable amplifier (CA)

interface. The Tx gain control select changes the interpretation

of the bits in Registers 0x13, 0x17, 0x1B, and 0x1F (see the

Cable Driver Gain Control section).

Bits 4–5: Profile Select

The AD9877 quadrature digital upconverter is capable of

storing four preconfigured modulation modes called profiles.

Each profile defines a transmit frequency tuning word and cable

driver amplifier gain (DAC gain) setting. Profile Select [1:0] bits

or PROFILE [1:0] pins program the current register profile to

be used. Profile Select bits should always be 0 if PROFILE[1:0]

pins are used to switch between profiles. Using the Profile Select

bits as a means of switching between different profiles requires

the PROFILE [1:0] pins to be tied low.

REGISTERS 0x10–0x1F—BURST PARAMETER

Tx Frequency Tuning Words

The frequency tuning word (FTW) determines the DDS-

generated carrier frequency (fC) and is formed via a

concatenation of register addresses.

The 26-bit FTW is spread over four register addresses. Bit 25 is

the MSB, and Bit 0 is the LSB.

The carrier frequency equation is given as

fc = [FTW × fSYSCLK]/226

where:

fSYSCLK = M × fOSCIN.

FTW < 0 × 2000000.

Changes to FTW bytes take effect immediately.

Cable Driver Gain Control

The AD9877 has a three-pin interface to the AD832x family of

programmable gain cable driver amplifiers. This allows direct

control of the cable driver’s gain through the AD9877.

In its default mode, the complete 8-bit register value is

transmitted over the 3-wire CA interface.

If Bit 3 of Register 0x0F is set high, Bits [7:4] determine the

8-bit word sent over the CA interface according to Table 7.

AD9877 Datasheet(PDF) 21 Page - Analog Devices

AD9877 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL