Step-Down Controllers with Prebias Startup,

Lossless Sensing, Synchronization, and OVP

______________________________________________________________________________________

25

Ω

Applications Information

PC Board Layout Guidelines

Careful PC board layout is critical to achieve low

switching losses and clean, stable operation. The

switching power stage requires particular attention.

Follow these guidelines for good PC board layout:

1) Place IC decoupling capacitors as close to IC pins

as possible. Keep separate the power ground

plane and the signal ground plane. Place the input

ceramic decoupling capacitor directly across and

as close as possible to the high-side MOSFET’s

drain and the low-side MOSFET’s source. This is to

help contain the high switching current within this

small loop.

2) For output current greater than 10A, a four-layer PC

board is recommended. Pour a signal ground

plane in the second layer underneath the IC to min-

imize noise coupling.

3) Connect input, output, snubber, and VL capacitors

to the power ground plane; connect all other

capacitors to the signal ground plane.

4) Place the inductor current-sense resistor and capaci-

tor as close to the inductor as possible. Make a

Kelvin connection to minimize the effect of PC board

trace resistance. Place the input bias balance resistor

and bypass capacitor (R5 and C10 in Figures 7 and

8) near CS-. Run two closely parallel traces from

across the capacitor (C9 in Figures 7 and 8) to CS+

and CS-. Place the decoupling capacitor C11 close

to CS+ and CS- pins.

5) Place the MOSFET as close as possible to the IC to

minimize trace inductance of the gate-drive loop. If

parallel MOSFETs are used, keep the trace lengths

to both gates equal.

6) Connect the drain leads of the power MOSFET to a

large copper area to help cool the device. Refer to

the power MOSFET data sheet for recommended

copper area.

7) Place the feedback and compensation components

as close to the IC pins as possible. Connect the

feedback-divider resistor from FB to the output as

close as possible to the farthest output capacitor.

Refer to the MAX8544 evaluation kit for an example layout.

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