DA6102 datasheet(77/82 Pages) DIALOG

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DA6102

6-Channel High Efficiency PMIC for 2-Cell Systems

Datasheet

Revision 2.1

28-Apr-2017

77 of 82

Table 14 : Channel 1, 2, and 4 Optional Compensation Settings

EA_CC

EA_HFGAIN

Comp. Zero (Hz)

HF Comp. Gain (dB)

698

1395

2790

5581

349

698

1395

2790

174

349

698

1395

174

349

698

Voltage Mode, Channel 3

Compensating Channel 3 follows a similar process to the current mode channels, with the addition of

the previously described register setting, CMP_VO3 (0x21). The Channel 3 optional compensation

registers are found at CMP3 (0x33). The goal for Channel 3 compensation is to set two

compensation zeroes around or just below the LC pole frequency. To accomplish this, first calculate

the LC pole frequency highlighted in the mod curve of Figure 44. Next, in Table 15 find the closest

Zero1 frequency equal or less than the LC pole frequency and set the EA_CC3 and EA_HFGAIN3

bits accordingly. In most cases there are several settings which result in the same Zero1 frequency.

Use the setting with the lowest gain initially as this will be the most stable (and lowest bandwidth).

Next set the Zero2 frequency with CMP_VO3 in Table 15 that most closely matches or is just below

the LC pole frequency.

The SLP_VO3 register at 0x20 controls the PWM ramp for Channel3, which determines the

modulator gain. In the rare case where the loop cannot be stabilized as described above, the overall

gain can be reduced by setting SLP_VO3 to 01.

DA6102 Datasheet(PDF) 77 Page - Dialog Semiconductor