BLUENRG-2 datasheet(47/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

47/190

Bit

Field name

Reset

Description

TCIF0

0x0

Channel 0 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 0.

1: A transfer complete (TC) occurred on channel 0.

HTIF0

0x0

Channel 0 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 0.

1: A half transfer (HT) event occurred on channel 0.

TEIF0

0x0

Channel 0 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 0.

1: A transfer error (TE) occurred on channel 0.

GIF1

0x0

Channel 1 global interrupt flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 1.

1: A TE, HT or TC event occurred on channel 1.

TCIF1

0x0

Channel 1 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 1.

1: A transfer complete (TC) occurred on channel 1.

HTIF1

0x0

Channel 1 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 1.

1: A half transfer (HT) event occurred on channel 1.

TEIF1

0x0

Channel 1 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 1.

1: A transfer error (TE) occurred on channel 1.

GIF2

0x0

Channel 2 global interrupt flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 2.

1: A TE, HT or TC event occurred on channel 2.

TCIF2

0x0

Channel 2 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 2.

1: A transfer complete (TC) occurred on channel 2.

BLUENRG-2 Datasheet(PDF) 47 Page - STMicroelectronics

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