BLUENRG-2 datasheet(8/190 Pages) STMICROELECTRONICS

8 / 190 page

List of tables

BlueNRG-2

8/190

DocID030675 Rev 2

Table 148: GPIO

– IC register description: address offset GPIO_BASE_ADDR+0x28 .........................120

Table 149: GPIO - MODE0 register description: address offset GPIO_BASE_ADDR+0x2C ................120

Table 150: GPIO

– MODE1 register description: address offset GPIO_BASE_ADDR+0x30................120

Table 151: GPIO

– MODE2 register description: address offset GPIO_BASE_ADDR+0x34................121

Table 152: GPIO

– MODE3 register description: address offset GPIO_BASE_ADDR+0x38................121

Table 153: GPIO

– DATS register description: address offset GPIO_BASE_ADDR+0x3C ..................121

Table 154: GPIO

– DATC register description: address offset GPIO_BASE_ADDR+0x40...................122

Table 155: GPIO - MFTX register description: address offset GPIO_BASE_ADDR+0x44....................122

Table 156: MFT modes...........................................................................................................................123

Table 157: MFT IO functions ..................................................................................................................130

Table 158: MFT interrupt functions .........................................................................................................131

Table 159: MFTX registers .....................................................................................................................132

Table 160: MFTX

– TNCNT1 register description: address offset MFTX_BASE_ADDR+0x00.............132

Table 161: MFTX

– TNCRA register description: address offset MFTX_BASE_ADDR+0x04 ..............132

Table 162: MFTX

– TNCRB register description: address offset MFTX_BASE_ADDR+0x08 ..............132

Table 163: MFTX

– TNCNT2 register description: address offset MFTX_BASE_ADDR+0x0C ............133

Table 164: MFTX

– TNPRSC register description: address offset MFTX_BASE_ADDR+0x10 ............133

Table 165: MFTX - TNCKC register description: address offset MFTX_BASE_ADDR+0x14 ...............133

Table 166: MFTX - TNMCTRL register description: address offset MFTX_BASE_ADDR+0x18 ..........133

Table 167: MFTX - TNICTRL register description: address offset MFTX_BASE_ADDR+0x1C ............134

Table 168: MFTX - TNICLR register description: address offset MFTX_BASE_ADDR+0x20...............135

Table 169: Watchdog interrupt interval...................................................................................................135

Table 170: WDG registers ......................................................................................................................136

Table 171: WDG - LR register description: address offset WDG_BASE_ADDR+0x00 .........................137

Table 172: WDG - VAL register description: address offset WDG_BASE_ADDR+0x04 .......................137

Table 173: WDG - CR register description: address offset WDG_BASE_ADDR+0x08.........................137

Table 174: WDG - ICR register description: address offset WDG_BASE_ADDR+0x0C .......................137

Table 175: WDG - RIS register description: address offset WDG_BASE_ADDR+0x10........................137

Table 176: WDG - MIS register description: address offset WDG_BASE_ADDR+0x14 .......................138

Table 177: WDG - LOCK register description: address offset WDG_BASE_ADDR+0xC00 .................138

Table 178: RTC modes...........................................................................................................................139

Table 179: RTC registers........................................................................................................................141

Table 180: RTC - CWDR register description: address offset RTC_BASE_ADDR+0x00 .....................141

Table 181: RTC - CWDMR register description: address offset RTC_BASE_ADDR+0x04 ..................142

Table 182: RTC - CWDLR register description: address offset RTC_BASE_ADDR+0x08 ...................143

Table 183: RTC - CWYR register description: address offset RTC_BASE_ADDR+0x0C .....................144

Table 184: RTC - CWYMR register description: address offset RTC_BASE_ADDR+0x10...................144

Table 185: RTC - CWYLR register description: address offset RTC_BASE_ADDR+0x14....................144

Table 186: RTC - CTCR register description: address offset RTC_BASE_ADDR+0x18.......................144

Table 187: RTC - IMSC register description: address offset RTC_BASE_ADDR+0x1C .......................145

Table 188: RTC - RIS register description: address offset RTC_BASE_ADDR+0x20...........................145

Table 189: RTC - MIS register description: address offset RTC_BASE_ADDR+0x24. .........................145

Table 190: RTC - ICR register description: address offset RTC_BASE_ADDR+0x28 ..........................145

Table 191: RTC

– TDR register description: address offset RTC_BASE_ADDR+0x2C........................146

Table 192: RTC - TCR register description: address offset RTC_BASE_ADDR+0x30 .........................146

Table 193: RTC

– TLR1 register description: address offset RTC_BASE_ADDR+0x34 .......................146

Table 194: RTC

– TLR2 register description: address offset RTC_BASE_ADDR+0x38 .......................147

Table 195: RTC

– TPR1 register description: address offset RTC_BASE_ADDR+0x3C ......................147

Table 196: RTC

– TPR2 register description: address offset RTC_BASE_ADDR+0x40.......................147

Table 197: RTC

– TPR3 register description: address offset RTC_BASE_ADDR+0x44.......................147

Table 198: RTC

– TPR4 register description: address offset RTC_BASE_ADDR+0x48.......................147

Table 199: RTC

– TIN register description: address offset RTC_BASE_ADDR+0x4C .........................147

Table 200: RNG registers .......................................................................................................................148

Table 201: RNG

– CR register description: address offset RNG_BASE_ADDR+0x00 .........................148

Table 202: RNG

– SR register description: address offset RNG_BASE_ADDR+0x04..........................148

BLUENRG-2 Datasheet(PDF) 8 Page - STMicroelectronics

BLUENRG-2 Datasheet(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL