BLUENRG-2 datasheet(10/190 Pages) STMICROELECTRONICS

10 / 190 page

List of figures

BlueNRG-2

10/190

DocID030675 Rev 2

List of figures

Figure 1: BlueNRG-2 architecture ............................................................................................................11

Figure 2: BlueNRG-2 bus architecture......................................................................................................12

Figure 3: BlueNRG-2 single chip RF software layers ...............................................................................13

Figure 4: BlueNRG-2 network processor RF software layers...................................................................14

Figure 5: BlueNRG-2 power management state machine........................................................................17

Figure 6: Clock tree...................................................................................................................................22

Figure 7: Reset and wakeup generation...................................................................................................23

Figure 8: BlueNRG-2 power-up sequence ...............................................................................................24

Figure 9: Reset circuit ...............................................................................................................................25

Figure 10: ADC block diagram..................................................................................................................31

Figure 11: DMA request mapping in BlueNRG-2 .....................................................................................46

Figure 12: MicroWire master and slave communication...........................................................................61

Figure 13: UART character frame.............................................................................................................70

Figure 14: Hardware flow control between two similar devices................................................................72

Figure 15: PWM signal............................................................................................................................124

Figure 16: MFT mode 1 block diagram ...................................................................................................124

Figure 17: MFT mode 1a block diagram.................................................................................................125

Figure 18: MFT mode 2 block diagram ...................................................................................................127

Figure 19: MFT mode 3 block diagram ...................................................................................................128

Figure 20: MFT mode 4 block diagram...................................................................................................129

Figure 21: BlueNRG-2 pin out top view (QFN32) ...................................................................................155

Figure 22: BlueNRG-2 pin out top view (QFN48) ...................................................................................156

Figure 23: BlueNRG-2 ball out top view (WCSP34) ...............................................................................157

Figure 24: BlueNRG-2 ball out bottom view (WCSP34) .........................................................................158

Figure 25: Application circuit: active DC-DC converter QFN32 package ...............................................163

Figure 26: Application circuit: non-active DC-DC converter QFN32 package........................................163

Figure 27: Application circuit: active DC-DC converter WCSP34 package............................................164

Figure 28: Application circuit: non active DC-DC converter WCSP34 package.....................................164

Figure 29: High speed oscillator block diagram......................................................................................174

Figure 30: QFN32 (5 x 5 x 1 pitch 0.5 mm) package outline ..................................................................180

Figure 31: QFN32 (5 x 5 x 1 pitch 0.5 mm) package detail "A" .............................................................181

Figure 32: QFN48 (|6 x 6 x 0.85 pitch 0.4 mm) package outline ............................................................182

Figure 33: WLCSP34 (2.66 x 2.56 x 0.5 pitch 0.4 mm) package outline................................................184

Figure 34: Flip Chip CSP (2.71 x 2.58 x 0.5 pitch 0.4 mm) package reflow profile recommendation ....186

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