BLUENRG-2 datasheet(28/190 Pages) STMICROELECTRONICS

28 / 190 page

Functional details

BlueNRG-2

28/190

DocID030675 Rev 2

Bit

Field name

Reset

Description

UART

0x1

UART clock

SPI

0x1

SPI clock

6:5

RESERVED

0x3

RESERVED

WDOG

0x1

Watchdog clock

ADC

0x1

ADC clock

I2C1

0x1

I2C1 clock

I2C2

0x1

I2C2 clock

MFT1

0x1

MFT1 clock

MFT2

0x1

MFT2 clock

RTC

0x1

RTC clock

15:14

RESERVED

0x3

RESERVED

DMA

0x1

DMA AHB clock

RNG

0x1

RNG AHB clock

PKA

0x0

PKA AHB clock

PKA RAM

0x0

PKA RAM clock

31:20

RESERVED

0x0

RESERVED

Table 19: CKGEN_SOC - DMA_CONFIG register description: address offset

CKGEN_SOC_BASE_ADDR+0x24

Bit

Field name

Reset

Description

ADC_CH0

0x0

Select ADC on DMA channel 0 instead of

peripheral

ADC_CH1

0x0

Select ADC on DMA channel 1 instead of

peripheral

ADC_CH2

0x0

Select ADC on DMA channel 2 instead of

peripheral

ADC_CH3

0x0

Select ADC on DMA channel 3 instead of

peripheral

ADC_CH4

0x0

Select ADC on DMA channel 4 instead of

peripheral

ADC_CH5

0x0

Select ADC on DMA channel 5 instead of

peripheral

ADC_CH6

0x0

Select ADC on DMA channel 6 instead of

peripheral

ADC_CH7

0x0

Select ADC on DMA channel 7 instead of

peripheral

31:8

RESERVED

0x0

RESERVED

BLUENRG-2 Datasheet(PDF) 28 Page - STMicroelectronics

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