BLUENRG-2 datasheet(6/190 Pages) STMICROELECTRONICS

6 / 190 page

List of tables

BlueNRG-2

6/190

DocID030675 Rev 2

Table 37: ADC - OFFSET register description: address offset ADC_BASE_ADDR+0x18 ......................38

Table 38: ADC - SR_REG register description: address offset ADC_BASE_ADDR+0x20 .....................38

Table 39: ADC - THRESHOLD_HI register description: address offset ADC_BASE_ADDR+0x24 ........39

Table 40: ADC - THRESHOLD_LO register description: address offset ADC_BASE_ADDR+0x28 .......39

Table 41: Programmable data width and endian behavior (when bits PINC = MINC = 1) .......................41

Table 42: DMA interrupt requests .............................................................................................................45

Table 43: DMA registers ...........................................................................................................................46

Table 44: DMA - ISR register description: address offset DMA_BASE_ADDR+0x00 .............................46

Table 45: DMA - IFCR register description: address offset DMA_BASE_ADDR+0x04 ...........................50

Table 46: DMA_CHx registers ..................................................................................................................54

Table 47: DMA_CHx - CCR register description: address offset DMA_CHX_BASE_ADDR+0x00 .........54

Table 48: DMA_CHx - CNDTR register description: address offset DMA_CHX_BASE_ADDR+0x04 ....55

Table 49: DMA_CHx - CPAR register description: address offset DMA_CHX_BASE_ADDR+0x08.......55

Table 50: DMA_CHx - CMAR register description: address offset DMA_CHX_BASE_ADDR+0x0C .....56

Table 51: SPI pin assignments .................................................................................................................56

Table 52: SPI clock phase and clock polarity ...........................................................................................57

Table 53: SPI_OUT endianness ...............................................................................................................58

Table 54: SPI_IN endianness ...................................................................................................................58

Table 55: SPI registers .............................................................................................................................61

Table 56: SPI - CR0 register description: address offset SPI_BASE_ADDR+0x00.................................62

Table 57: SPI - CR1 register description: address offset SPI_BASE_ADDR+0x04.................................63

Table 58: SPI - DR register description: address offset SPI_BASE_ADDR+0x08...................................65

Table 59: SPI - SR register description: address offset SPI_BASE_ADDR+0x0C ..................................65

Table 60: SPI - CPSR register description: address offset SPI_BASE_ADDR+0x10 ..............................65

Table 61: SPI - IMSC register description. Address offset SPI_BASE_ADDR+0x14. .............................65

Table 62: SPI - RIS register description: address offset SPI_BASE_ADDR+0x18 ..................................66

Table 63: SPI - MIS register description: address offset SPI_BASE_ADDR+0x1C .................................66

Table 64: SPI - ICR register description: address offset SPI_BASE_ADDR+0x20..................................67

Table 65: SPI - DMACR register description: address offset SPI_BASE_ADDR+0x24...........................67

Table 66: SPI

– RXFRM register description: address offset SPI_BASE_ADDR+0x28 ..........................67

Table 67: SPI

– CHN register description: address offset SPI_BASE_ADDR+0x2C...............................67

Table 68: SPI

– WDTXF register description: address offset SPI_BASE_ADDR + 0x30 ........................68

Table 69: SPI - ITCR register description: address offset SPI_BASE_ADDR+0x80 ...............................68

Table 70: SPI

– TDR register description: address offset SPI_BASE_ADDR+0x8C ...............................68

Table 71: RX FIFO errors .........................................................................................................................69

Table 72: Typical baud rates with OVSFACT = 0.....................................................................................71

Table 73: Typical baud rates with OVSFACT = 1.....................................................................................71

Table 74: Control bits to enable and disable hardware flow control .........................................................72

Table 75: Control bits to enable and program receive software flow control............................................73

Table 76: Control bits to enable and program transmit software flow control ..........................................74

Table 77: UART registers .........................................................................................................................76

Table 78: UART - DR register description: address offset UART_BASE_ADDR+0x00...........................78

Table 79: UART - RSR register description: address offset UART_BASE_ADDR+0x04 ........................78

Table 80: UART - TIMEOUT register description: address offset UART_BASE_ADDR+0x0C ...............79

Table 81: UART - FR register description: address offset UART_BASE_ADDR+0x18 ...........................79

Table 82: UART - LCRH_RX register description: address offset UART_BASE_ADDR+0x1C ..............80

Table 83: UART - IBRD register description: address offset UART_BASE_ADDR+0x24 .......................81

Table 84: UART - FBRD register description: address offset UART_BASE_ADDR+0x28 ......................81

Table 85: UART - LCRH_TX register description: address offset UART_BASE_ADDR+0x2C...............81

Table 86: UART - CR register description: address offset UART_BASE_ADDR+0x30...........................82

Table 87: UART - IFLS register description: address offset UART_BASE_ADDR+0x34 ........................84

Table 88: UART - IMSC register description: address offset UART_BASE_ADDR+0x38 .......................84

Table 89: UART - RIS register description: address offset UART_BASE_ADDR+0x3C .........................85

Table 90: UART - MIS register description: address offset UART_BASE_ADDR+0x40 .........................86

Table 91: UART - ICR register description: address offset UART_BASE_ADDR+0x44..........................87

BLUENRG-2 Datasheet(PDF) 6 Page - STMicroelectronics

BLUENRG-2 Datasheet(HTML) 6 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL