BLUENRG-2 datasheet(5/190 Pages) STMICROELECTRONICS

5 / 190 page

BlueNRG-2

List of tables

DocID030675 Rev 2

5/190

List of tables

Table 2: BlueNRG-2 interrupt vectors.......................................................................................................15

Table 3: Relationship between BlueNRG-2 states and functional blocks ................................................19

Table 4: SYSTEM_CTRL registers ...........................................................................................................19

Table 5: SYSTEM_CTRL - WKP_IO_IS register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x00 ......................................................................................................20

Table 6: SYSTEM_CTRL - WKP_IO_IE register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x04 ......................................................................................................20

Table 7: SYSTEM_CTRL - CTRL register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x08 ......................................................................................................20

Table 8: SYSTEM_CTRL - SLEEPIO_OEN register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x0C .....................................................................................................20

Table 9: SYSTEM_CTRL

– SLEEPIO_OUT register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x10 ......................................................................................................21

Table 10: SYSTEM_CTRL - SLEEPIO_DS register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x14 ......................................................................................................21

Table 11: SYSTEM_CTRL - SLEEPIO_PE register description: address offset

SYSTEM_CTRL_BASE_ADDR+0x18 ......................................................................................................21

Table 12: AHBUPCONV registers ............................................................................................................21

Table 13: BLUE_CTRL registers ..............................................................................................................21

Table 14: CKGEN_SOC registers ............................................................................................................26

Table 15: CKGEN_SOC - CONTROL register description: address offset

CKGEN_SOC_BASE_ADDR+0x00 .........................................................................................................27

Table 16: CKGEN_SOC - REASON_RST register description: address offset

CKGEN_SOC_BASE_ADDR+0x08 .........................................................................................................27

Table 17: CKGEN_SOC - DIE_ID register description: address offset

CKGEN_SOC_BASE_ADDR+0x1C .........................................................................................................27

Table 18: CKGEN_SOC - CLOCK_EN register description: address offset

CKGEN_SOC_BASE_ADDR+0x20 .........................................................................................................27

Table 19: CKGEN_SOC - DMA_CONFIG register description: address offset

CKGEN_SOC_BASE_ADDR+0x24 .........................................................................................................28

Table 20: CKGEN_SOC - JTAG_IDCODE register description: address offset

CKGEN_SOC_BASE_ADDR+0x28 .........................................................................................................29

Table 21: CKGEN_BLE registers .............................................................................................................29

Table 22: CKGEN_BLE - REASON_RST register description: address offset

CKGEN_BLE_BASE_ADDR+0x08 ..........................................................................................................29

Table 23: CKGEN_BLE - CLK32K_COUNT register description: address offset

CKGEN_BLE_BASE_ADDR+0x0C ..........................................................................................................30

Table 24: CKGEN_BLE - CLK32K_PERIOD register description: address offset

CKGEN_BLE_BASE_ADDR+0x10 ..........................................................................................................30

Table 25: CKGEN_BLE - CLK32K_FREQ register description: address offset

CKGEN_BLE_BASE_ADDR+0x14 ..........................................................................................................30

Table 26: CKGEN_BLE - CLK32K_IT register description: address offset

CKGEN_BLE_BASE_ADDR+0x18 ..........................................................................................................31

Table 27: ADC channels ...........................................................................................................................32

Table 28: ADC data rate ...........................................................................................................................32

Table 29: ADC parameters settings..........................................................................................................32

Table 30: Output data rate with microphone ............................................................................................33

Table 31: ADC registers............................................................................................................................35

Table 32: ADC - CTRL register description: address offset ADC_BASE_ADDR+0x00 ...........................35

Table 33: ADC - CONF register description: address offset ADC_BASE_ADDR+0x04 ..........................36

Table 34: ADC - IRQSTAT register description: address offset ADC_BASE_ADDR+0x08.....................37

Table 35: ADC - IRQMASK register description: address offset ADC_BASE_ADDR+0x0C ...................38

Table 36: ADC - DATA_CONV register description: address offset ADC_BASE_ADDR+0x14 ..............38

BLUENRG-2 Datasheet(PDF) 5 Page - STMicroelectronics

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