BLUENRG-2 datasheet(7/190 Pages) STMICROELECTRONICS

7 / 190 page

BlueNRG-2

List of tables

DocID030675 Rev 2

7/190

Table 92: UART - DMACR register description: address offset UART_BASE_ADDR+0x48 ..................88

Table 93: UART - XFCR register description: address offset UART_BASE_ADDR+0x50 ......................88

Table 94: UART - XON1 register description: address offset UART_BASE_ADDR+0x54 ......................89

Table 95: UART - XON2 register description. Address offset UART_BASE_ADDR+0x58. ....................89

Table 96: UART - XOFF1 register description. Address offset UART_BASE_ADDR+0x5C. ..................89

Table 97: UART - XOFF2 register description. Address offset UART_BASE_ADDR+0x60....................89

Table 98: I2Cx registers............................................................................................................................92

Table 99: I2C - CR register description: address offset I2CX_BASE_ADDR+0x00.................................93

Table 100: I2C - SCR register description: address offset I2CX_BASE_ADDR+0x04 ............................94

Table 101: I2C2 - MCR register description: address offset I2CX_BASE_ADDR+0x0C .........................95

Table 102: I2C - TFR register description: address offset I2CX_BASE_ADDR+0x10.............................96

Table 103: I2C - SR register description: address offset I2CX_BASE_ADDR+0x14 ...............................96

Table 104: I2C - RFR register description: address offset I2CX_BASE_ADDR+0x18 ............................98

Table 105: I2C - TFTR register description: address offset I2CX_BASE_ADDR+0x1C ..........................98

Table 106: I2C - RFTR register description: address offset I2CX_BASE_ADDR+0x20 ..........................98

Table 107: I2C - DMAR register description: address offset I2CX_BASE_ADDR+0x24 .........................98

Table 108: I2C - BRCR register description: address offset I2CX_BASE_ADDR+0x28..........................99

Table 109: I2C - IMSCR register description: address offset I2CX_BASE_ADDR+0x2C .......................99

Table 110: I2C - RISR register description: address offset I2CX_BASE_ADDR+0x30 .........................101

Table 111: I2C - MISR register description: address offset I2CX_BASE_ADDR+0x34.........................104

Table 112: I2C - ICR register description: address offset I2CX_BASE_ADDR+0x38............................105

Table 113: I2C - THDDAT register description: address offset I2CX_BASE_ADDR+0x4C ..................106

Table 114: I2C - THDSTA_FST_STD register description: address offset I2CX_BASE_ADDR+0x50 .106

Table 115: I2C - TSUSTA_FST_STD register description: address offset I2CX_BASE_ADDR+0x58 .106

Table 116: Flash commands ..................................................................................................................110

Table 117: Flash interface timing............................................................................................................110

Table 118: FLASH controller registers....................................................................................................110

Table 119: FLASH

– COMMAND register description: address offset FLASH_BASE_ADDR+0x00 ....111

Table 120: FLASH

– CONFIG register description: address offset FLASH_BASE_ADDR+0x04 .........111

Table 121: FLASH - IRQSTAT register description: address offset FLASH_BASE_ADDR+0x08 ........111

Table 122: FLASH - IRQMASK register description: address offset FLASH_BASE_ADDR+0x0C .......112

Table 123: FLASH - IRQRAW register description: address offset FLASH_BASE_ADDR+0x10 .........112

Table 124: FLASH

– SIZE register description: address offset FLASH_BASE_ADDR+0x14 ...............112

Table 125: FLASH

– ADDRESS register description: address offset FLASH_BASE_ADDR+0x18 ......112

Table 126: FLASH

– LFSRVAL register description: address offset FLASH_BASE_ADDR+0x24 .......112

Table 127: FLASH

– TIMETRIM1 register description: address offset FLASH_BASE_ADDR+0x28 ....112

Table 128: FLASH

– TIMETRIM2 register description: address offset FLASH_BASE_ADDR+0x2C ...113

Table 129: FLASH

– TIMETRIM3 register description: address offset FLASH_BASE_ADDR+0x30....113

Table 130: FLASH

– DATA0 register description: address offset FLASH_BASE_ADDR+0x40............113

Table 131: FLASH

– DATA1 register description: address offset FLASH_BASE_ADDR+0x44............113

Table 132: FLASH

– DATA2 register description: address offset FLASH_BASE_ADDR+0x48............113

Table 133: FLASH

– DATA3 register description: address offset FLASH_BASE_ADDR+0x4C ...........113

Table 134: IO functional map..................................................................................................................114

Table 135: GPIO interrupt modes...........................................................................................................115

Table 136: Pin characteristics.................................................................................................................115

Table 137: IO pull values ........................................................................................................................116

Table 138: GPIO registers ......................................................................................................................117

Table 139: GPIO

– DATA register description: address offset GPIO_BASE_ADDR+0x00 ...................118

Table 140: GPIO

– OEN register description: address offset GPIO_BASE_ADDR+0x04.....................118

Table 141: GPIO

– PE register description: address offset GPIO_BASE_ADDR+0x08........................119

Table 142: GPIO

– DS register description: address offset GPIO_BASE_ADDR+0x0C .......................119

Table 143: GPIO

– IS register description: address offset GPIO_BASE_ADDR+0x10 .........................119

Table 144: GPIO

– IBE register description: address offset GPIO_BASE_ADDR+0x14.......................119

Table 145: GPIO

– IEV register description: address offset GPIO_BASE_ADDR+0x18.......................119

Table 146: GPIO

– IE register description: address offset GPIO_BASE_ADDR+0x1C.........................119

Table 147: GPIO

– MIS register description: address offset GPIO_BASE_ADDR+0x24 ......................119

BLUENRG-2 Datasheet(PDF) 7 Page - STMicroelectronics

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