DP83815 datasheet(49/108 Pages) NSC

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4.0 Register Set (Continued)

4.2.8 Interrupt Enable Register

The Interrupt Enable Register controls the hardware INTR signal.

4.2.9 Transmit Descriptor Pointer Register

This register points to the current Transmit Descriptor.

Tag: IER

Size: 32 bits

Hard Reset: 00000000h

Offset: 0018h

Access: Read Write

Soft Reset: 00000000h

Bit

Bit Name

Description

31-1

unused

Interrupt Enable

When set to 1, the hardware INTR signal is enabled. When set to 0, the hardware INTR signal will be

masked, and no interrupts will be generated. The setting of this bit has no effect on the ISR or IMR. This

provides the ability to disable the hardware interrupt to the host with a single access (eliminating the

need for a read-modify-write cycle).

Tag: TXDP

Size: 32 bits

Hard Reset: 00000000h

Offset: 0020h

Access: Read Write

Soft Reset: 00000000h

Bit

Bit Name

Description

31-2

TXDP

Transmit Descriptor Pointer

The current value of the transmit descriptor pointer. When the transmit state machine is idle, software

must set TXDP to the address of a completed transmit descriptor. While the transmit state machine is

active, TXDP will follow the state machine as it advances through a linked list of active descriptors. If the

link field of the current transmit descriptor is NULL (signifying the end of the list), TXDP will not advance,

but will remain on the current descriptor. Any subsequent writes to the TXE bit of the CR register will

cause the transmit state machine to reread the link field of the current descriptor to check for new

descriptors that may have been appended to the end of the list. Transmit descriptors must be aligned on

an even 32-bit boundary in host memory (A1-A0 must be 0).

1-0

unused

DP83815 Datasheet(PDF) 49 Page - National Semiconductor (TI)

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