DP83815 datasheet(86/108 Pages) NSC

86 / 108 page

5.0 Buffer Management (Continued)

www.national.com

5.3 Receive Architecture

The receive architecture is as "symmetrical" to the transmit

architecture as possible. The receive buffer manager

prefetches receive descriptors to prepare for incoming

packets. When the amount of receive data in the

RxDataFIFO is more than the RxDrainThreshold, or the

RxDataFIFO contains a complete packet, then the state

machine begins filling received buffers in host memory.

Figure 5-6 Receive Architecture

When the RXE bit is set to 1 in the CR register (regardless

of the current state), and the DP83815 receive state

machine is idle, then DP83815 will read the contents of the

descriptor referenced by RXDP into the Rx Descriptor

Cache. The Rx Descriptor Cache allows the DP83815 to

read an entire descriptor in a single burst, and reduces the

number of bus accesses required for fragment information

to 1. The DP83815 Rx Descriptor Cache holds a single

buffer pointer/count combination.

5.3.1 Receive State Machine

The receive state machine has the following states:

The receive state machine manipulates the following internal data spaces:

Inputs to the receive state machine include the following events:

Receive Descriptor List

Rx Descriptor Cache

Software/Memory

Hardware

Rx Data FIFO

link

cmdsts

ptr

Rx DMA

cmdsts

RxHead

link

cmdsts

ptr

link

cmdsts

ptr

rxIdle

The receive state machine is idle.

rxDescRefr

Waiting for the "refresh" transfer of the link field of a completed descriptor from the PCI bus.

rxDescRead

Waiting for the transfer of a descriptor from the PCI bus into the RxDescCache.

rxFifoBlock

Waiting for the amount of data in the RxDataFifo to reach the RxDrainThreshold or to represent a

complete packet.

rxFragWrite

Waiting for the transfer of data from the RxDataFIFO via the PCI bus to host memory.

rxDescWrite

Waiting for the completion of the write of the cmdsts field of a receive descriptor.

RXDP

A 32-bit register that points to the current receive descriptor.

CRDD

An internal bit flag that is set when the current receive descriptor has been completed, and ownership

has been returned to the driver. It is cleared whenever RXDP is loaded with a new value (either by the

state machine, or the driver).

RxDescCache An internal data space equal to the size of the maximum receive descriptor supported.

descCnt

Count of bytes available for storing receive data in all fragments described by the current descriptor.

fragPtr

Pointer to the next unwritten byte in the current fragment.

rxPktCnt

Number of packets in the rxDataFifo. Incremented by the MAC (the fill side of the FIFO). Decremented

by the receive state machine as packets are processed.

rxPktBytes

Number of bytes in the current packet being drained from the rxDataFifo, that are in fact currently in the

rxDataFifo (Note: packets larger than FIFO size, this number will never be greater than the FIFO size).

CR:RXE

The RXE bit in the Command Register has been set.

XferDone

completion of a PCI bus transfer request.

FifoReady

(rxPktCnt > 0) or (rxPktBytes > rxDrainThreshold)... in other words, if we have a complete packet in the

FIFO (regardless of size), or the number of bytes that we do have is greater than the rxDrainThreshold,

then we are ready to begin draining the rxDataFifo.

DP83815 Datasheet(PDF) 86 Page - National Semiconductor (TI)

DP83815 Datasheet(HTML) 86 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL