AD8452 datasheet(32/35 Pages) AD

32 / 35 page

Data Sheet

AD8452

Rev. 0 | Page 31 of 34

SETTING THE OPERATING FREQUENCY AND

PROGRAMMING THE SYNCHONIZATION PIN

Operating modes of the AD8452 clock rely on the state of the

FREQ pin and one of three possible voltage options applied to

the SCFG pin. See Table 10 for a summary of synchronization

options.

When the voltage at the SCFG pin exceeds 4.53 V (or the pin is

floating and internally connected to VREG), the AD8452 operates

at the frequency set by RFREQ. The SYNC pin is configured as an

output, displaying a clock signal at the programmed frequency. In

this state, the clock voltage at the SYNC pin can be used as a

master clock for synchronized applications.

If VSCFG is ≤0.5 V, the SYNC pin is configured as an input, and

the AD8452 operates as a slave device. As a slave device, the

AD8452 synchronizes to the external clock applied to the SYNC

pin. If the voltage applied to the SCFG pin is 0.65 V < VSCFG <

4.25 V, and a resistor is connected between SCFG and ground,

the SYNC pin is configured as an input, and the AD8452

synchronizes to a phase shifted version of the external clock

applied to the SYNC pin.

Whether operating the AD8452 as a master or as a slave device,

carefully select RFREQ using the equations in the following sections.

Select RFREQ for Standalone or Master Clock

Whether master or slave, the clock frequency can be selected

graphically or by applying Equation 4.

Figure 26 shows the relationship between the RFREQ (MASTER) value

and the programmed switching frequency. Simply identify the

desired clock frequency on Axis fSET, and read the

corresponding resistor value on Axis RFREQ (MASTER).

To calculate the RFREQ (MASTER) value for a desired master clock

synchronization frequency, use the following equation:

( )

(kHz)

kΩ

)

(

SET

MASTER

FREQ

(4)

where RFREQ (MASTER) is the resistor in kΩ to set the frequency for

the master device, and fSET is the switching frequency in kHz.

Selecting RFREQ for a Slave Device

To configure the AD8452 as a slave device, drive VSCFG < 4.53 V,

and the device operates at the frequency of an external clock

applied to the SYNC pin. To ensure proper synchronization,

select RFREQ to set the frequency to a value slightly slower than

that of the master clock by using the following equation:

RFREQ (SLAVE) = 1.11 × RFREQ (MASTER)

(5)

where RFREQ (SLAVE) is the resistor value that appropriately scales

the frequency for the slave device, 1.11 is the RFREQ slave to

master ratio for synchronization and RFREQ (MASTER) is the resistor

value of the master clock applied to the SYNC pin.

The frequency of the slave device is set to a frequency slightly

lower than that of the master device to allow the digital

synchronization loop of the AD8452 to synchronize to the

master clock period. The slave device can synchronize to a

master clock frequency running from 2% to 20% higher than

the slave clock frequency. Setting RFREQ(SLAVE) to 1.11× larger than

RFREQ(MASTER) runs the synchronization loop in approximately the

center of the adjustment range.

Programming the External Clock Phase Shift

If a phase shift is not required for slave devices, connect the

SCFG pin of each slave device to ground. For devices that

require a phase shifted version of the synchronization clock that

is applied to the SYNC pin of the slave devices, connect a

resistor (RSCFG) from SCFG to ground to program the desired

phase shift. To determine the RSCFG value for a desired phase

shift (φSHIFT), start by calculating the frequency of the slave clock

(fSLAVE).

(SLAVE)

FREQ

SLAVE

(kHz) =

(6)

Next, calculate the period of the slave clock.

(kHz)

(

SLAVE

(7)

where:

tSLAVE is the period of the slave clock in µs.

fSLAVE is the frequency of the slave clock in kHz.

Next, determine the phase time delay (tDELAY) for the desired

phase shift (φSHIFT) using the following equation:

( )

360

μs

(

SHIFT

SLAVE

(8)

where:

tDELAY is the phase time delay in µs.

φSHIFT is the desired phase shift.

Lastly, use the following equation to calculate tDELAY:

RSCFG (kΩ) = 0.45 × RFREQ(SLAVE) (kΩ) + 50 × tDELAY (µs)

(9)

where:

RSCFG is the corresponding resistor for the desired phase shift in

kHz. See Figure 27 for the RSCFG vs. tDELAY graph.

When using the phase shift feature, connect a capacitor of 47 pF

or greater in parallel with RSCFG.

Alternatively, the SCFG pin can be controlled with a voltage source

but if an independent voltage source is used, ensure VSCFG ≤ VREG

under all conditions. When the AD8452 is disabled via UVLO,

VREG = 0 V, and the voltage source must be adjusted accordingly

to ensure VSCFG ≤ VREG.

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