AD8452 datasheet(21/35 Pages) AD

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AD8452

Data Sheet

Rev. 0 | Page 20 of 34

In-Amp Offset Option

As shown in Figure 35, the in-amp reference node is connected

to the ISREFL pin and ISREFH pin via an internal resistor divider.

This resistor divider can be used to introduce a temperature

insensitive offset to the output of the in-amp such that it always

reads a voltage higher than zero for a zero differential input.

Because the output voltage of the in-amp is always positive, a

unipolar analog-to-digital converter (ADC) can digitize it.

When the ISREFH pin is tied to the VREF pin with the ISREFL

pin grounded, the voltage at the ISMEA pin is increased by an

offset voltage, VOS, of 12.5 mV, guaranteeing that the output of

the in-amp is always positive for zero differential inputs. Other

voltage shifts can be realized by tying the ISREFH pin to an

external voltage source. The gain from the ISREFH pin to the

ISMEA pin is 5 mV/V. For zero offset, connect the ISREFL pin

and ISREFH pin to ground.

Battery Reversal and Overvoltage Protection

The AD8452 in-amp can be configured for high-side or low-side

current sensing. If the in-amp is configured for high-side

current sensing (see Figure 34) and the battery is connected

backward, the in-amp inputs may be held at a voltage that is below

the negative power rail (AVEE), depending on the battery voltage.

To prevent damage to the in-amp under these conditions, the

in-amp inputs include overvoltage protection circuitry that

allows them to be held at voltages of up to 55 V from the

opposite power rail. In other words, the safe voltage span for the

in-amp inputs extends from AVCC − 55 V to AVEE + 55 V.

DIFFERENCE AMPLIFIER

Figure 36 is a block diagram of the difference amplifier used to

monitor the battery voltage. The architecture of the difference

amplifier is a subtractor amplifier with a fixed gain of 0.4 V/V.

This gain value allows the difference amplifier to funnel the

voltage of a 5 V battery to a level that can be read by a 5 V ADC

with a 4.096 V reference.

BVREFL

BVP

BVN

200kΩ

80kΩ

79.7kΩ

AD8452 DIFFAMP

BVREFH

VREF

BVMEA

300Ω

60kΩ

CONNECT

FOR VOS

OF 12.5mV

+ BATTERY

TERMINAL

– BATTERY

TERMINAL

Figure 36. Difference Amplifier Simplified Block Diagram

The resistors that form the difference amplifier gain network

are laser trimmed to a matching level better than ±0.1%. This

level of matching minimizes the gain error and gain error drift

of the difference amplifier while maximizing the CMRR of the

difference amplifier. This matching also allows the controller to

set a stable target voltage for the battery over temperature while

rejecting the ground bounce in the battery negative terminal.

Like the in-amp, the difference amplifier can also level shift its

output voltage via an internal resistor divider that is tied to the

difference amplifier reference node. This resistor divider is

connected to the BVREFH pin and BVREFL pin.

When the BVREFH pin is tied to the VREF pin with the BVREFL

pin grounded, the voltage at the BVMEA pin is increased by

12.5 mV, guaranteeing that the output of the difference amplifier is

always positive for zero differential inputs. Other voltage offsets

are realized by tying the BVREFH pin to an external voltage

source. The gain from the BVREFH pin to the BVMEA pin is

5 mV/V. For zero offset, tie the BVREFL pin and the BVREFH pin

to ground.

CC AND CV LOOP FILTER AMPLIFIERS

The CC and CV loop filter amplifiers are high precision, low

noise specialty amplifiers with very low offset voltage and very

low input bias current. These amplifiers serve two purposes:

•

Using external components, the amplifiers implement active

loop filters that set the dynamics (transfer function) of the

CC and CV loops.

•

The amplifiers perform a seamless transition from CC to

CV mode after the battery reaches its target voltage.

Figure 37 is a functional block diagram of the AD8452 CC and

CV feedback loops for charge mode (the MODE pin is logic high).

For illustrative purposes, the external networks connected to

the loop amplifiers are simple RC networks configured to form

single-pole inverting integrators. This type of configuration

exhibits very high dc precision when the feedback loop is

closed, due to the high loop gain when the feedback loop is in

place. The outputs of the CC and CV loop filter amplifiers are

internally connected to the VINT pins via an analog NOR

circuit (minimum output selector circuit), such that they can only

pull the VINT node down. In other words, the loop amplifier that

requires the lowest voltage at the VINT pins is in control of the

node. Thus, only one loop, CC or CV, can be in control of the

system charging control loop at any given time. When the loop

is inactive (open, such as when the EN pin is low), the voltage at

the VINT pins must be railed at AVCC.

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