AD8452 datasheet(25/35 Pages) AD

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AD8452

Data Sheet

Rev. 0 | Page 24 of 34

For optimum protection from switching and other ambient

noise, all of these supply pins must be bypassed to ground with

high quality ceramic capacitors (X7R or better), located as near

as possible to the device.

VREG is an internal 5 V supply that powers the control circuitry

including all the current sources for user selected PWM features. It

is active as long as VIN is above the internal UVLO (5.75 V

typical). VREG may be used as a pull-up voltage for the MODE,

SYNC, DMAX, and FAULT pins and any other external pull-ups as

long as the additional current does not exceed 5 mA. Bypass the

VREG pin to ground with a 1 μF ceramic capacitor.

SHUTDOWN

The EN input turns the AD8452 PWM section on or off and

can operate from voltages up to 60 V. When the EN voltage is less

than 1.2 V (typical), the PWM shuts down, and DL and DH are

driven low. When the PWM shuts down, the VIN supply current is

15 μA (typical). When the EN voltage is greater than 1.26 V

(typical), the PWM is enabled.

In addition to the EN pin, the PWM is disabled via a fault

condition flagged by an TSD, an undervoltage lockout (UVLO)

condition on VIN, or an external fault condition via the FAULT

pin.

When changing the operating mode, it is necessary to disable

the AD8452 by setting the EN pin low.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO function prevents the PWM from turning on until

voltage VIN ≥ 5.75 V (typical). The UVLO enable state has

~410 mV of hysteresis to prevent the PWM from turning on

and off repeatedly if the supply voltage to the VIN pin ramps

slowly. The UVLO disables the PWM when VIN drops below

5.34 V (typical).

SOFT START

The AD8452 has a programmable soft start that prevents output

voltage overshoot during startup. When the EN pin goes high,

an internal 5 μA current source connected to the SS pin begins

charging the external capacitor, CSS, that is connected to VREG

(5 V), creating a linear voltage ramp (VSS) that controls several

time sensitive PWM control functions.

When VSS < 0.52 V (typical), the DH and DL logic outputs are

both low. When VSS exceeds 0.52 V (typical), nonsynchronous

switching is enabled, either the DH pin or the DL pin logic

output become active, and the PWM duty cycle gradually

increases. When VSS > 4.5 V (typical), synchronous switching

is enabled (see Figure 43 and Figure 44

4.5V

0.52V

SYNCHRONOUS OPERATION

ENABLED AT ~90% RAMP

PWM SWITCHING

ENABLED AT ~10% RAMP

BEGIN

RAMP

EN GOES HIGH

DL FOLLOWS

DH BEGINS

Figure 43. DH and DL Sequence in Charge Mode

DL FOLLOWS

DH BEGINS

SYNCHRONOUS OPERATION

ENABLED AT ~90% RAMP

PWM SWITCHING

ENABLED AT ~10% RAMP

EN GO ES HIGH

4.5V

0.52V

BEGIN

RAMP

Figure 44. DH and DL Sequence in Discharge Mode

In conjunction with the MODE pin, the VSS ramp also

establishes when the DH and DL, logic outputs and thus the

output FET switches, become active. In charge mode (Mode

high), the pulse sequence at the DH pin precedes that at the DL

pin. Conversely, in discharge mode, the sequence is reversed

and the DL pin precedes the DH pin.

The duty cycle of the DH and DL drive pins increase in

proportion to the ramp level, reducing the output voltage

overshoot during startup (see the Selecting CSS section).

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