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AD8452 Datasheet(PDF) 6 Page - Analog Devices

Part # AD8452
Description  Precision Integrated Analog Front End, Controller
PDF  35 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD8452 Datasheet(HTML) 6 Page - Analog Devices

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Data Sheet
AD8452
Rev. 0 | Page 5 of 34
PULSE-WIDTH MODULATOR SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SOFT START (SS)
SS Pin Current
VSS = 0 V
4
5
6
µA
SS Threshold Rising
Switching enable threshold
0.52
0.65
V
SS Threshold Falling
Switching disable threshold
0.4
0.5
V
End of Soft Start
Asynchronous to synchronous threshold
4.4
4.5
4.6
V
PWM CONTROL
Frequency
Frequency Range
RFREQ = 33.2 kΩ to 200 kΩ
50
300
kHz
Oscillator Frequency
RFREQ = 100 kΩ
90
100
110
kHz
FREQ Pin Voltage
RFREQ = 100 kΩ
1.1
1.255
1.4
V
SYNC Output (Internal Frequency
Control)
VSCFG ≥ 4.53 V or SCFG pin floating
Internal SYNC Range
For SYNC output
50
300
kHz
SYNC Output Clock Duty Cycle
VSCFG = VVREG, RFREQ = 100 kΩ
40
50
60
%
SYNC Sink Pull Down Resistance
VSCFG = 5 V, ISYNC = 10 mA
10
20
Ω
SYNC Input (External Frequency Control)
VSCFG < 4.25 V
External SYNC Range
For SYNC input clock
50
300
kHz
SYNC Internal Pull-Down Resistor
0.5
1
1.5
MΩ
Maximum SYNC Pin Voltage
For external sync operation
5
V
SYNC Threshold Rising
1.2
1.5
V
SYNC Threshold Falling
0.7
1.05
V
SCFG
SCFG High Threshold
Rising
SYNC set to input
4.53
4.7
V
Falling
SYNC set to output
4.25
4.47
V
SCFG Low Threshold
Rising
Programmable phase shift above threshold
0.55
0.65
V
Falling
No phase shift
0.4
0.5
V
SCFG Pin Current
RFREQ = 100 kΩ, VSCFG = DGND
10
11
12
µA
DMAX
Maximum Internal Duty Cycle
VDMAX, VSS, and VSCFG = 5 V
97
%
DMAX Setting Current
VDMAX = 0 V, RFREQ = 100 kΩ
10
11
12
µA
DMAX and SCFG Current Matching1
10
%
DT
DT Pin Current
RFREQ = 100 kΩ, VDT = DGND
20
24
µA
Maximum DT Programming Voltage
See Figure 28
3.5
V
CURRENT LIMIT (CL)
CLVT
CLVT Pin Current
Minimum CLVT pin voltage = 50 mV
16
21
27
µA
CLP, CLN
Common-Mode Range
VCLP = VCLN
0
8
V
Input Resistance
24
30
36
kΩ
Current Limit Threshold Offset
VCLP = VCLN, RCLVT = 2.49 kΩ
50
mV
CLFLG
Open-drain, active low output
Max CLFLG Voltage
Open-drain output
5.5
V
CFLG Pull-Down Resistance
8
Ω
Current Limit
RFREQ = 100 kΩ, 16 consecutive clock pulses
Overload Time
160
μs
Cool Down Time
160
μs



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