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AD8452

Data Sheet

Rev. 0 | Page 18 of 34

THEORY OF OPERATION

INTRODUCTION

Lithium ion (Li-Ion) batteries require an elaborate and time

consuming postproduction process known as forming. Battery

formation consists of a series of charge/discharge cycles that

require precise current and voltage control and monitoring. The

AD8452 provides not only the stringent current and voltage

accuracy requirements, but also a highly accurate PWM, with

logic level DH and DL outputs ready for a half-H bridge configured

switch mode power output converter—all in a highly compact

7 mm × 7 mm package.

The analog front end of the AD8452 includes a precision current

sense in-amp with gain of 66× ±0.1% and a precision voltage

sense difference amplifier with a gain of 0.4 × ±0.1% for battery

voltage.

As shown in Figure 38, the AD8452 provides constant CC/CV

charging technologies, with transparent internal switching

between the two. Typical systems induce predetermined levels

of current into or out of the battery until the voltage reaches a

target value. At this point, a set constant voltage is applied

across the battery terminals, reducing the charge current until

reaching zero.

The AD8452 features a complete PWM including on-board

user adjustable features such as clock frequency, duty cycle,

clock phasing, current limiting, soft start timing, and

multichannel synchronization.

Figure 33 is the block diagram of the AD8452, illustrating the

distinct sections of the AD8452, including the in-amp and

difference amplifier measurement blocks, loop filter amplifiers,

and PWM.

Figure 34 is a block diagram of the AD8452 integrated within a

battery formation and test system. The AD8452 is usable over a

wide range of current and voltage applications simply by

judicious selection of a current sense shunt, selected according

to system requirements.

ISVP

VREG = 5V

ISVN

AVEE

ISREFH

ISREFLS

ISREFL

AVCC

BVREFH

BVPS

BVREFL

BVP

BVNS

BVREFLS

BVN

500Ω

100kΩ

BATTERY

CURRENT

SENSE IA

G = 66

MODE_B

300Ω

60kΩ

VIN

SCFG

VREG

FREQ

DGND

SYNC

1MΩ

1×

80kΩ

200kΩ

SS DISCHARGE

8.5MΩ

200kΩ

SCFG

CONFIG

DETECT

1×

SYNC

SYNC DETECT

AVEE

AVCC

BATTERY

VOLTAGE

SENSE DA

G = 0.4

AVEE

CLFLG

AVCC

DMAX

VREG

DMAX

MODE'

CLFLG

SYNC

OSCILLATOR

VREG

UVLO

TSD

BAND

GAP

MODE_B

5µA

+/–

79.7kΩ

2.5V

VREF

1MΩ

CURRENT LIMIT

AND DIODE

EMULATION

MODE_B

CV LOOP

FILTER

AMPLIFIER

SOFT START

AMPLIFIER

1.1mA

CC LOOP

FILTER

AMPLIFIER

VCTRL

COMP

IDMAX

11µA

ISCFG

11µA

VBG = 1.252V

MODE_B

DRIVE

LOGIC

0.3µA

1.64pF

10µA

20µA

VFREQ = 1.252V

Figure 33. AD8452 Detailed Block Diagram

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