AD8452 datasheet(27/35 Pages) AD

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AD8452

Data Sheet

Rev. 0 | Page 26 of 34

PEAK CURRENT LIMITING

AND DIODE EMULATION

VREG

(CLP – CLN)

VREG

MODE

CLVT

ICLVT = 20µA

RCLVT

1mV

AD8452

DUTY CYCLE DH

DUTY CYCLE DL

CUR LIM

SYNC OFF

CLN

CLP

+DCBUS

VRCL

RCL

IRCL

VBAT

RSH

VCLVT

+ –

Figure 47. Peak Current Limiting and Diode Emulation Block Diagram

The threshold voltage for the peak current comparator is user

adjustable by connecting a resistor from the current-limit voltage

threshold (CLVT pin) to ground. The AD8452 generates this

voltage from a 20 μA current source (see the Select RCL and RCLVT

for the Peak Current Limit section).

Diode Emulation/Synchronous Mode Operation

The RCL current sense resistor is also used to detect and control

current reversal. When the voltage across RCL drops to

−5 mV ≤ VRCL ≤ +5 mV (for charge and discharge modes) during

the synchronous FET switching cycle, the synchronous FET is

turned off to stop the flow of reverse current.

Information on how to set the current limit and the current sense

resistor RCL is available in the Applications Information section.

2.5A

2.5A p-p

DH AND DL WITH INDUCTOR CURRENT

WHILE IN CHARGE MODE

DIODE

EMULATION

BEGINS

INDUCTOR

CURRENT

Figure 48. Diode Emulation in Charge Mode, Low Charge Current Required

FREQUENCY AND PHASE CONTROL

The FREQ, SYNC, and SCFG pins determine the source,

frequency, and synchronization of the clock signal that operates

the PWM control of the AD8452.

Internal Frequency Control

The AD8452 frequency can be programmed with an external

resistor connected between FREQ and ground. The frequency

range can be set from a minimum of 50 kHz to a maximum of

300 kHz. If the SCFG pin is tied to VREG, forcing VSCFG ≥ 4.53 V

(typical), or if the SCFG pin is left floating, the SYNC pin is

configured as an output, and the AD8452 operates at the

frequency set by RFREQ, which outputs from the SYNC pin through

the open-drain device. The output clock of the SYNC pin operates

with a 50% (typical) duty cycle. In this configuration, the SYNC

pin can synchronize other switching regulators in the system to

the AD8452. When the SYNC pin is configured as an output, an

external pull-up resistor is needed from the SYNC pin to an

external supply. The VREG pin of the AD8452 can be used as

the external supply rail for the pull-up resistor.

External Frequency Control

When VSCFG ≤ 0.5 V (typical), the SYNC pin is configured as an

input, the AD8452 synchronizes to the external clock applied to

the SYNC pin, and the AD8452 operates as a slave device. This

synchronization allows the AD8452 to operate at the same

switching frequency with the same phase as other switching

regulators or devices in the system. When operating the AD8452

with an external clock, select RFREQ to provide a frequency that

approximates but is not equal to the external clock frequency,

which is further explained in the Applications Information

section.

Operating Frequency Phase Shift

When the voltage applied to the SCFG pin is 0.65 V < VSCFG <

4.25 V, the SYNC pin is configured as an input, and the AD8452

synchronizes to a phase shifted version of the external clock

applied to the SYNC pin. To adjust the phase shift, place a resistor

(RSCFG) from SCFG to ground. The phase shift can be used to

reduce the input supply ripple for systems containing multiple

switching power supplies.

MAXIMUM DUTY CYCLE

Referring to Figure 52, the maximum duty cycle of the AD8452

can be externally programmed for any value between 0% and 97%

by installing a resistor from the DMAX pin to ground. The

maximum duty cycle defaults to 97% if the DMAX pin is left

floating or connected to 5 V (the VREG pin).

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