AD8452 datasheet(23/35 Pages) AD

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AD8452

Data Sheet

Rev. 0 | Page 22 of 34

1. At turn on, the default start-up voltages at the ISMEA pin

and BVMEA pin are both zero, and both integrators (loop

amplifiers) begin to ramp, increasing the voltage at the

VINT node. (The voltage at the VINT pin always rises

following an enable regardless of mode setting).

2. As the voltage at the VINT node increases, the output

current IBAT from the power converter starts to rise.

3. When the IBAT current reaches the target CC steady state

value IBAT, the battery voltage is considerably less than the

target steady state value, VBAT. Therefore, the CV loop

amplifier forces its output voltage high enough to disconnect

itself from VINT. The CC loop prevails, maintaining the

target charge current until the target VBAT is achieved and

the CC loop stops integrating.

4. Due to the analog OR circuit, the loop amplifiers can only

pull the VINT node down. The CC loop takes control of

the charging feedback loop, and the CV loop is disabled.

5. As the charging process continues, the battery voltage

increases until it reaches the steady state value, VBAT, and

the voltage at the BVMEA pin reaches the target voltage, VVSET.

6. The CV loop tries to pull the VINT node down to reduce

the charging current (IBAT) and prevent the battery voltage

from rising any further. At the same time, the CC loop tries

to keep the VINT node at its current voltage to keep the

battery current at IBAT.

7. Because the loop amplifiers can only pull the VINT node

down due to the analog NOR circuit, the CV loop takes

control of the charging feedback loop, and the CC loop is

disabled.

The analog OR (minimum output selector) circuit that couples

the outputs of the loop amplifiers is optimized to minimize the

transition time from CC to CV control. Any delay in the transition

causes the CC loop to remain in control of the charge feedback

loop after the battery voltage reaches its target value. Therefore,

the battery voltage continues to rise beyond VBAT until the

control loop transitions; that is, the battery voltage overshoots

its target voltage. When the CV loop takes control of the charge

feedback loop, it reduces the battery voltage to the target voltage.

A large overshoot in the battery voltage due to transition delays

can damage the battery; thus, it is crucial to minimize delays by

implementing a fast CC to CV transition.

Figure 39 is the functional block diagram of the AD8452 CC

and CV feedback loops for discharge mode (MODE logic pin is

low). In discharge mode, the feedback loops operate in a similar

manner as in charge mode. The only difference is in the CV

loop amplifier, which operates as a noninverting integrator in

discharge mode. For illustration purposes, the external networks

connected to the loop amplifiers are simple RC networks

configured to form single-pole integrators.

ISET

CC LOOP

AMPLIFIER

CV LOOP

AMPLIFIER

IVE0

ISMEA

BVMEA

VVSET

VSET

MODE

VINT

HALF BRIDGE

AND LPF

MIN

OUTPUT

SELECT

VVE0

VVP0

VSET

BUFFER

VSETB

1×

–

66×

0.4×

AC IAC

HALF BRIDGE

DRIVER

PWM

INVERTER

12V DC

BAT

–

VISET

SHUNT

IBAT

ISVN

BVP

ISVP

BVN

Figure 39. Functional Block Diagram of the CC and CV Loops in Discharge Mode (MODE Pin Low)

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