AD8452 datasheet(24/35 Pages) AD

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Data Sheet

AD8452

Rev. 0 | Page 23 of 34

Compensation

In battery formation and test systems, the CC and CV feedback

loops have significantly different open-loop gain and crossover

frequencies; therefore, each loop requires its own frequency

compensation. The active filter architecture of the AD8452 CC

and CV loops allows the frequency response of each loop to be

set independently via external components. Moreover, due to

the internal switches in the CC and CV amplifiers, the frequency

response of the loops in charge mode does not affect the

frequency response of the loops in discharge mode.

Unlike simpler controllers that use passive networks to ground for

frequency compensation, the AD8452 allows the use of feedback

networks for its CC and CV loop filter amplifiers. These networks

enable the implementation of both proportional differentiator (PD)

Type II and proportional integrator differentiator (PID) Type III

compensators. Note that in charge mode, both the CC and CV

loops implement inverting compensators, whereas in discharge

mode, the CC loop implements an inverting compensator, and

the CV loop implements a noninverting compensator. As a result,

the CV loop in discharge mode includes an additional amplifier,

the VSET buffer, to buffer the VSET node from the feedback

network VINT buffer.

CHARGE AND DISCHARGE CONTROL

Conditions to Charge and Discharge a Battery

Battery charging and discharging requires separate paradigms in

terms of the analog requirements and the PWM configurations.

These paradigms are based on manufacturer provided information,

most importantly the C rating where C is simply the battery

capacity expressed in ampere hours. For example, if the battery is

C rated as 10 Ah, and the charge rate is specified as 0.2 C, the

charge current is 2 A for a duration of 5 hours.

To charge, the applied voltage must be greater than the voltage of

the battery under charge and the current must not exceed the

manufacturers specification, usually expressed as a fraction of the

full C rating. When discharging, the opposite conditions apply;

the discharge voltage must be less than the unloaded battery

voltage, and the current flows out of the battery, reversing the

polarity of the shunt voltage.

Multiple charge/discharge sequences can last for days at a time

before the battery achieves its optimum storage capacity, and

the charge/discharge currents and voltages must be accurately

monitored.

MODE Pin

The MODE pin is a logic level input that selects charge with a

logic high (VMODE > 2 V) or discharge with a logic low (VMODE <

0.8 V). All the analog and PWM circuitry for charging and

discharging of the battery is configured and is latched in when

the EN pin goes high.

The MODE pin controls the polarity of the internal analog loop

and the DH/DL sequence. In charge mode, DH precedes DL; in

discharge mode, DL precedes DH.

When the AD8452 operates in charge mode, the PWM operates

in a buck configuration. In discharge mode, the configuration

changes to boost. See Figure 40 and Figure 41 for the AD8452

DH and DL behavior in each mode. On the rising edge of EN, the

state of the MODE pin is latched, preventing the mode of operation

from being changed while the device is enabled. To change between

charge and discharge modes of operation, shut down or disable the

AD8452, adjust the MODE pin to change the operating mode, and

reenable the system.

The operating mode can be changed when the EN pin is driven

low, the FAULT pin is driven low, or the AD8452 is disabled via

a TSD event or UVLO condition. On the rising edge of the FAULT

control signal, the state of the MODE pin is latched, preventing

the mode of operation from being changed while the device is

enabled.

4.5V

VREG

(5V TYP)

0.5V

PIN DL

2.5V (TYP)

PIN DH

INTERNAL RAMP

(4V p-p)

VREG

(5V TYP)

DH AND DL IN CHARGE MODE

Figure 40. DH and DL Output Waveforms for Charge Mode

4.5V

VREG

(5V TYP)

0.5V

PIN DL

2.5V (TYP)

PIN DH

INTERNAL RAMP

(4V p-p)

VREG

(5V TYP)

DH AND DL IN DISCHARGE MODE

Figure 41. DH and DL Output Waveforms for Discharge Mode

INPUT AND OUTPUT SUPPLY PINS

The AD8452 has five power supply input pins, a pair each of the

internally connected AVCC pin and AVEE pin for the analog

section and Input VIN for the PWM section. The maximum

supply voltage for the VIN pin is 60 V; if operating with an

input voltage greater than 50 V, see Figure 42 for recommended

additional input filtering.

SUPPLY > 50V

AD8452

4.7µF

VIN

Figure 42. Recommended Filter Configuration for

Input Voltages Greater Than 50 V

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