AD9271 datasheet(40/61 Pages) AD

40 / 61 page

AD9271

Rev. B | Page 39 of

Addr.

(Hex)

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

Notes/

Comments

test_io

User test mode

00 = off (default)

01 = on, single alternate

10 = on, single once

11 = on, alternate once

Reset PN

long gen

1 = on

0 = off

(default)

Reset PN

short

gen

1 = on

0 = off

(default)

Output test mode—see

Table 10

0000 = off (default)

0001 = midscale short

0010 = +FS short

0011 = −FS short

0100 = checkerboard output

0101 = PN sequence long

0110 = PN sequence short

0111 = one-/zero-word toggle

1000 = user input

1001 = 1-/0-bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency (format

determined by output_mode)

0x00

When this

the test data is

placed on the

output pins in

place of normal

data. (Local,

expect for

PN sequence.)

flex_channel_input

Filter cutoff frequency control

0000 = 1.3 × 1/3 × fSAMPLE

0001 = 1.2 × 1/3 × fSAMPLE

0010 = 1.1 × 1/3 × fSAMPLE

0011 = 1.0 × 1/3 × fSAMPLE

0100 = 0.9 × 1/3 × fSAMPLE

0101 = 0.8 × 1/3 × fSAMPLE

0110 = 0.7 × 1/3 × fSAMPLE

0x30

Antialiasing

filter cutoff

(global).

flex_offset

6-bit LNA offset adjustment

011001 = 50 MSPS speed grade

011010 = 40 MSPS speed grade

011111 = 25 MSPS speed grade

0x20

LNA force

offset

correction

(local).

flex_gain

LNA gain

00 = 5×

01 = 6×

10 = 8×

0x01

LNA gain

adjustment

(global).

output_mode

0 = LVDS

ANSI-644

(default)

1 = LVDS

low power,

(IEEE

1596.3

similar)

Output

invert

1 = on

0 = off

(default)

00 = offset binary

(default)

01 = twos

complement

0x00

Configures the

outputs and

the format of

the data.

output_adjust

Output driver

termination

00 = none (default)

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

DCO±

and

FCO±

2× drive

strength

1 = on

0 = off

(default)

0x00

Determines

LVDS or other

output prop

erties. Primarily

functions to set

the LVDS span

and common-

mode levels in

place of an

external

resistor.

output_phase

0011 = output clock phase adjust

(0000 through 1010)

(Default: 180° relative to data edge)

0000 = 0° relative to data edge

0001 = 60° relative to data edge

0010 = 120° relative to data edge

0011 = 180° relative to data edge

0100 = 240° relative to data edge

0101 = 300° relative to data edge

0110 = 360° relative to data edge

0111 = 420° relative to data edge

1000 = 480° relative to data edge

1001 = 540° relative to data edge

1010 = 600° relative to data edge

1011 to 1111 = 660° relative to data edge

0x03

On devices that

utilize global

clock divide,

determines

which phase of

the divider

output is used

to supply the

output clock.

Internal

latching

is unaffected.

AD9271 Datasheet(PDF) 40 Page - Analog Devices

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