AD9271 datasheet(30/61 Pages) AD

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AD9271

Rev. B | Page 29 of

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter. IF undersampling applications

are particularly sensitive to jitter (see Figure 59).

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9271.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources, such as the Valpey Fisher VFAC3 series.

If the clock is generated from another type of source (by gating,

dividing, or other methods), it should be retimed by the

original clock during the last step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about how

jitter performance relates to ADCs (visit www.analog.com).

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.5ps

10 BITS

8 BITS

1.0ps

2.0ps

ANALOG INPUT FREQUENCY (MHz)

RMS CLOCK JITTER REQUIREMENT

0.25ps

Figure 59. Ideal SNR vs. Input Frequency and Jitter

Power Dissipation and Power-Down Mode

As shown in Figure 61, the power dissipated by the AD9271 is

proportional to its sample rate. The digital power dissipation

does not vary much because it is determined primarily by the

DRVDD supply and bias current of the LVDS output drivers

(Figure 60).

800

SAMPLING FREQUENCY (MSPS)

700

600

500

400

300

200

100

IDRVDD

IAVDD, 50MSPS SPEED GRADE

IAVDD, 40MSPS SPEED GRADE

IAVDD, 25MSPS SPEED GRADE

Figure 60. Supply Current vs. fSAMPLE for fIN = 7.5 MHz

190

100

SAMPLING FREQUENCY (MSPS)

180

170

160

150

140

130

120

110

50MSPS SPEED GRADE

40MSPS SPEED GRADE

25MSPS SPEED GRADE

Figure 61. Power per Channel vs. fSAMPLE for fIN = 7.5 MHz

By asserting the PDWN pin high, the AD9271 is placed into

power-down mode. In this state, the device typically dissipates

2 mW. During power-down, the LVDS output drivers are placed

into a high impedance state. The AD9271 returns to normal

operating mode when the PDWN pin is pulled low. This pin is

both 1.8 V and 3.3 V tolerant.

By asserting the STBY pin high, the AD9271 is placed into a

standby mode. In this state, the device typically dissipates

65 mW. During standby, the entire part is powered down except

the internal references. The LVDS output drivers are placed into

a high impedance state. This mode is well suited for applications

that require power savings because it allows the device to be

powered down when not in use and then quickly powered up.

The time to power the device back up is also greatly reduced. The

AD9271 returns to normal operating mode when the STBY pin

is pulled low. This pin is both 1.8 V and 3.3 V tolerant.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode: shorter cycles result in proportionally shorter wake-up

times. To restore the device to full operation, approximately

1 ms is required when using the recommended 0.1 μF and 4.7 μF

decoupling capacitors on the REFT and REFB pins and the

0.01 μF decoupling capacitors on the GAIN± pins. Most of this

time is dependent on the gain decoupling; higher value decoupling

capacitors on the GAIN± pins result in longer wake-up times.

There are a number of other power-down options available

when using the SPI port interface. The user can individually

power down each channel or put the entire device into standby

mode. This allows the user to keep the internal PLL powered up

when fast wake-up times are required. The wake-up time is

slightly dependent on gain. To achieve a 1 μs wake-up time

when the device is in standby mode, 0.5 V must be applied to

the GAIN± pins. See the Memory Map section for more details

on using these features.

AD9271 Datasheet(PDF) 30 Page - Analog Devices

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