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AD9271

Rev. B | Page 28 of

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9271 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional bias.

Figure 54 shows the preferred method for clocking the AD9271.

A low jitter clock source, such as the Valpey Fisher oscillator

VFAC3-BHL-50MHz, is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9271 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9271, and it preserves the

fast rise and fall times of the signal, which are critical to low

jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

0.1µF

3.3V

Ω 100Ω

CLK–

CLK+

ADC

AD9271

MINI-CIRCUITS

ADT1-1WT, 1:1Z

XFMR

VFAC3

OUT

Figure 54. Transformer-Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a

differential PECL signal to the sample clock input pins as shown

in Figure 55. The AD951x family of clock drivers offers excellent

jitter performance.

100

Ω

0.1µF

240

Ω

240

Ω

AD951x FAMILY

Ω*

CLK

*50

Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9271

PECL DRIVER

3.3V

OUT

VFAC3

100

Ω

0.1µF

Figure 55. Differential PECL Sample Clock

LVDS DRIVER

CLK

*50

Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9271

AD951x FAMILY

3.3V

OUT

VFAC3

Ω*

Figure 56. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be driven directly from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 57). Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages of up to 3.3 V, making the

selection of the drive logic voltage very flexible.

0.1µF

39k

Ω

CMOS DRIVER

Ω*

OPTIONAL

100

Ω

0.1µF

CLK

*50

Ω RESISTOR IS OPTIONAL.

CLK–

CLK+

ADC

AD9271

AD951x FAMILY

3.3V

OUT

VFAC3

Figure 57. Single-Ended 1.8 V CMOS Sample Clock

0.1µF

CMOS DRIVER

Ω*

OPTIONAL

100

Ω

CLK

*50

Ω RESISTOR IS OPTIONAL.

0.1µF

CLK–

CLK+

ADC

AD9271

AD951x FAMILY

3.3V

OUT

VFAC3

Figure 58. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to the clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9271 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9271. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. However,

some applications may require the DCS function to be off. If so,

keep in mind that the dynamic range performance can be affected

when operated in this mode. See the Memory Map section for

more details on using this feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately eight clock cycles

to allow the DLL to acquire and lock to the new rate.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency (fA)

due only to aperture jitter (tJ) can be calculated by

SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]

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