AD9671EBZ datasheet(45/61 Pages) AD

45 / 61 page

AD9675

Data Sheet

Rev. A | Page 44 of 60

Figure 61. Serial Timing Details

Table 29. Serial Timing Definitions

Parameter

Timing (ns min)

Description

tDS

12.5

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK must be in a logic high state

tLOW

Minimum period that SCLK must be in a logic low state

tEN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling

edge (not shown in Figure 61)

tDIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising

edge (not shown in Figure 61)

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

SDIO

SCLK

CSB

tDH

tHIGH

tCLK

tLOW

tDS

R/W

A12

A11

A10

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