XRT75R03D datasheet(89/134 Pages) EXAR

89 / 134 page

XRT75R03D

THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCRONIZER

REV. 1.0.2

JA RESET Ch_n

R/W

Jitter Attenuator RESET - Channel_n:

Writing a "0 to 1" transition within this bit-field will configure

the Jitter Attenuator (within Channel_n) to execute a

RESET operation.

Whenever the user executes a RESET operation, then all

of the following will occur.

• The READ and WRITE pointers (within the Jitter

Attenuator FIFO) will be reset to their default values.

• The contents of the Jitter Attenuator FIFO will be

flushed.

NOTE: The user must follow up any "0 to 1" transition with

the appropriate write operate to set this bit-field

back to "0", in order to resume normal operation

with the Jitter Attenuator.

JA1 Ch_n

R/W

Jitter Attenuator Configuration Select Input - Bit 1:

This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is

used to do any of the following.

• To enable or disable the Jitter Attenuator corresponding

to Channel_n.

• To select the FIFO Depth for the Jitter Attenuator within

Channel_n.

The relationship between the settings of these two bit-

fields and the Enable/Disable States, and FIFO Depths is

presented below.

JA in Tx Path Ch_n

R/W

Jitter Attenuator in Transmit/Receive Path Select Bit:

This input pin is used to configure the Jitter Attenuator

(within Channel_n) to operate in either the Transmit or

Receive path, as described below.

0 - Configures the Jitter Attenuator (within Channel_n) to

operate in the Receive Path.

1 - Configures the Jitter Attenuator (within Channel_n) to

operate in the Transmit Path.

JA0 Ch_n

R/W

Jitter Attenuator Configuration Select Input - Bit 0:

Please see the description for Bit 2 (JA1 Ch_n).

BIT NUMBER

NAME

TYPE

DEFAULT

VALUE

DESCRIPTION

JA0

JA1

Jitter Attenuator Mode

Jitter Attenuator Disabled

SONET/SDH De-Sync Mode

FIFO Depth = 32 bits

FIFO Depth = 16 bits

XRT75R03D Datasheet(PDF) 89 Page - Exar Corporation

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