BCM4356 datasheet(28/155 Pages) CYPRESS

28 / 155 page

Document Number: 002-15053 Rev. *D

Page 28 of 155

ADVANCE

CYW4356

7. Bluetooth Peripheral Transport Unit

7.1 SPI Interface

The CYW4356 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates can be possible. The

physical interface between the SPI master and the CYW4356 consists of the four SPI signals (SPI_CSB, SPI_CLK, SPI_SI, and

SPI_SO) and one interrupt signal (SPI_INT). The SPI signals are muxed onto the UART signals, see Table 7. The CYW4356 can be

configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-

low or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian

or big-endian. Additionally, proprietary sleep mode and half-duplex handshaking is implemented between the SPI master and the

CYW4356. The SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle

of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data

lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in the higher layer protocols.

7.2 SPI/UART Transport Detection

The BT_HOST_WAKE (BT_GPIO1) pin is also used for BT transport detection. The transport detection occurs during the power-up

sequence. It selects either UART or SPI transport operation based on the following pin state:

■ If the BT_HOST_WAKE (BT_GPIO1) pin is pulled low by an external pull-down during power-up, it selects the SPI transport interface.

■ If the BT_HOST_WAKE (BT_GPIO1) pin is not pulled low externally during power-up, then the default internal pull-up is detected

as a high and it selects the UART transport interface.

When the A4WP feature is not used and USB is selected as the Bluetooth interface to the host, an external pull-up (outside the chip)

10 KΩ resistor to BT_VDDIO is required. The pull-up is not necessary but is recommended when the Bluetooth/host interface is UART

instead of USB.

7.3 PCM Interface

The CYW4356 supports two independent PCM interfaces that share the pins with the I2S interfaces. The PCM Interface on the

CYW4356 can connect to linear PCM codec devices in master or slave mode. In master mode, the CYW4356 generates the PCM_CLK

and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to

the CYW4356.

The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands.

7.3.1 Slot Mapping

The CYW4356 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three

channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample

interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or

1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM

data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow

other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM

clock during the last bit of the slot.

7.3.2 Frame Synchronization

The CYW4356 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization

mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is

synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the

first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization

signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident

with the first bit of the first slot.

Table 7. SPI to UART Signal Mapping

SPI Signals

UART Signals

SPI_CLK

UART_CTS_N

SPI_CSB

UART_RTS_N

SPI_MISO

UART_TXD

SPI_MOSI

UART_RXD

SPI_INT

BT_DEV_WAKE

BCM4356 Datasheet(PDF) 28 Page - Cypress Semiconductor

BCM4356 Datasheet(HTML) 28 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL