LTC3704 datasheet(9/28 Pages) LINER

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LTC3704

sn3704 3704fs

OPERATIO

minimum on-time (about 175ns). Below this output

current level, the converter will begin to skip cycles in

order to maintain output regulation. Figures 3 and 4 show

the light load switching waveforms for Burst Mode and

Pulse-Skip Mode operation for the converter in Figure 1.

Burst Mode Operation

Burst Mode operation is selected by leaving the MODE/

SYNC pin unconnected or by connecting it to ground. In

normal operation, the range on the ITH pin corresponding

to no load to full load is 0.30V to 1.2V. In Burst Mode

operation, if the error amplifier EA drives the ITH voltage

below 0.525V, the buffered ITH input to the current com-

parator C1 will be clamped at 0.525V (which corresponds

to 25% of maximum load current). The inductor current

peak is then held at approximately 30mV divided by the

power MOSFET RDS(ON). If the ITH pin drops below 0.30V,

the Burst Mode comparator B1 will turn off the power

MOSFET and scale back the quiescent current of the IC to

250

µA(sleepmode).Inthiscondition,theloadcurrentwill

be supplied by the output capacitor until the ITH voltage

rises above the 50mV hysteresis of the burst comparator.

At light loads, short bursts of switching (where the aver-

age inductor current is 25% of its maximum value) fol-

lowed by long periods of sleep will be observed, thereby

greatly improving converter efficiency. Oscilloscope wave-

forms illustrating Burst Mode operation are shown in

Figure 3.

buffered ITH burst clamp is removed, allowing the ITH pin

to directly control the current comparator from no load to

full load. With no load, the ITH pin is driven below 0.30V,

the power MOSFET is turned off and sleep mode is

invoked. Oscilloscope waveforms illustrating this mode of

operation are shown in Figure 4.

µs/DIV

3704 F03

Figure 3. LTC3704 Burst Mode Operation

(MODE/SYNC = 0V) at Low Output Current

Figure 4. LTC3704 Low Output Current Operation with Burst

Mode Operation Disabled (MODE/SYNC = INTVCC)

VOUT

50mV/DIV

5A/DIV

MODE/SYNC = 0V

(Burst Mode OPERATION)

VOUT

50mV/DIV

5A/DIV

MODE/SYNC = INTVCC

(PULSE-SKIP MODE)

µs/DIV

3704 F04

When an external clock signal drives the MODE/SYNC pin

at a rate faster than the chip’s internal oscillator, the

oscillator will synchronize to it. In this synchronized mode,

Burst Mode operation is disabled. The constant frequency

associated with synchronized operation provides a more

controlled noise spectrum from the converter, at the

expense of overall system efficiency of light loads.

When the oscillator’s internal logic circuitry detects a

synchronizing signal on the MODE/SYNC pin, the internal

oscillator ramp is terminated early and the slope compen-

sation is increased by approximately 30%. As a result, in

applications requiring synchronization, it is recommended

that the nominal operating frequency of the IC be pro-

grammed to be about 75% of the external clock frequency.

Attempting to synchronize to too high an external fre-

quency (above 1.3fO) can result in inadequate slope com-

pensation and possible subharmonic oscillation (or jitter).

The external clock signal must exceed 2V for at least 25ns,

and should have a maximum duty cycle of 80%, as shown

in Figure 5. The MOSFET turn on will synchronize to the

rising edge of the external clock signal.

Pulse-Skip Mode Operation

With the MODE/SYNC pin tied to a DC voltage above 2V,

Burst Mode operation is disabled. The internal, 0.525V

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