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LTC3704 Datasheet(PDF) 23 Page - Linear Technology |
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LTC3704 Datasheet(HTML) 23 Page - Linear Technology |
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23 / 28 page ![]() 23 LTC3704 sn3704 3704fs APPLICATIO S I FOR ATIO PC Board Layout Checklist 1. In order to minimize switching noise and improve output load regulation, the GND pin of the LTC3704 should be connected directly to 1) the negative termi- nal of the INTVCC decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the source of the power MOSFET or the bottom terminal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane immediately adjacent to Pin 6. The ground trace on the top layer of the PC board should be as wide and short as possible to minimize series resistance and induc- tance. LTC3704 M1 VIN 3704 F?? VOUT L1 RT RC CC1 R3 CIN COUT CVCC R1 R2 PSEUDO-KELVIN SIGNAL GROUND CONNECTION TRUE REMOTE OUTPUT SENSING VIAS TO GROUND PLANE R4 PIN 1 COUT D1 L2 CDC C3 CC2 1 2 3 4 5 6 12 11 10 9 8 7 Figure 22. LTC3704 Positive-to-Negative Converter Suggested Layout RUN ITH NFB FREQ MODE/ SYNC SENSE VIN INTVCC GATE GND LTC3704 R4 10 9 8 7 6 1 2 3 4 5 CVCC PSEUDO-KELVIN GROUND CONNECTION CIN M1 D1 L1 VIN GND 3704 F23 COUT RC R1 RT BOLD LINES INDICATE HIGH CURRENT PATHS R2 CC1 R3 C3 L2 CDC VOUT CC2 Figure 23. LTC3704 Positive-to-Negative Converter Layout Diagram |
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