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OV6130 Datasheet(PDF) 28 Page - List of Unclassifed Manufacturers |
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OV6130 Datasheet(HTML) 28 Page - List of Unclassifed Manufacturers |
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28 / 29 page ![]() SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS March 4, 2000 Version 1.0 28 COML[2] – Tristate all control signal output (FODD, CHSYNC, HREF, PCLK) COML[1] – Highest 1 bit of horizontal sync starting position, combined with register [3A] COML[0] – Highest 1 bit of horizontal sync ending position, combined with register [3B] 3A HSST 0F RW Horizontal sync start position HSST[7:0] – lower 8 bit of horizontal sync starting position, combined with register bit of COML[1], total 9 bit control. range: [00] -- [FF]. HSEND[8:0] must be less than HSST[8:0] 3B HSEND 3C RW Horizontal sync end position HEND[7:0] – lower 8 bit of horizontal sync ending position, combined with register bit of COML[0], total 9 bit control. range: [00] - [FF]. HSEND[8:0] must be larger than HSST[8:0] 3C COMM 21 RW Common control M COMM[7:5] – reserved. COMM[4] – AEC/AGC change mode selection COMM[3] – AEC/AGC change mode selection COMM[2] – AEC/AGC change fastest mode COMM[1] – AEC/AGC change fast mode COMM[0] – AEC/AGC change slowest mode 3D COMN 08 RW Common Control N COMN[7] – Enable one frame drop when AEC change to keep data valid when Banding filter mode enable. COMN[6:4] – reserved COMN[3] – Enable 50 Hz PAL video timing, VTO analog signal can be displayed on TV COMN[2] – reserved COMN[1] – Tri-state Y and UV digital video ports in power down mode. COMN[0] – reserved 3E COMO 80 RW Common control O COMO[7] – Input main clock divided by 2 or 4 selection. “1” -- 2; “0” -- 4 COMO[6:5] – reserved COMO[4] – Select 4-bit nibble mode output COMO[3] – reserved COMO[2] – Enable Minimum exposure time is 4 line. Default is 1 line COMO[1:0] – reserved 3F COMP 02 RW Common control P COMP[7] – reserved COMP[6] – Output main clock output from FODD port COMP[5] – reserved COMP[4] – Soft chip power down enable, can be waked up by disable this bit COMP[3:2] – reserved COMP[1] – ITU-656 output control COMP[0] – Reset internal timing circuit without reset AEC/AGC/AWB value 40-4C Rsvd 40-4C ×× – Reserved 4D YMXA 02 RW YUV matrix control (Main) YMXA[7:5] – reserved YMXA[4:3] – YUV/YCrCB selection: “00” U = u, V = v “01” U = 0.938u, V = 0.838v “10” U = 0.563u, V = 0.714v “11” U = 0.5u, V = 0.877v YMXA[2:0] – Reserved Note: This function is not available on the OV6130 image sensor. 4E ARL A0 RW AEC/AGC reference level ARL[7:5] – Voltage reference selection (Higher voltage = brighter final stable image) “000” = Lowest reference level “111” = Highest reference level ARL[4:0] – Reserved |
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